mirror of
https://github.com/AsahiLinux/u-boot
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a2ac2b964b
This converts the following to Kconfig: CONFIG_SKIP_LOWLEVEL_INIT CONFIG_SKIP_LOWLEVEL_INIT_ONLY In order to do this, we need to introduce SPL and TPL variants of these options so that we can clearly disable these options only in SPL in some cases, and both instances in other cases. Signed-off-by: Tom Rini <trini@konsulko.com>
205 lines
4.8 KiB
ArmAsm
205 lines
4.8 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* armboot - Startup Code for XScale CPU-core
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*
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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
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* Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
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* Copyright (C) 2001 Marius Groger <mag@sysgo.de>
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* Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
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* Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
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* Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
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* Copyright (C) 2003 Kshitij <kshitij@ti.com>
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* Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
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* Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
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* Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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*/
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#include <asm-offsets.h>
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#include <config.h>
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* setup Memory and board specific bits prior to relocation.
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* relocate armboot to ram
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* setup stack
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*
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*************************************************************************
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*/
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.globl reset
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reset:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0,cpsr
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bic r0,r0,#0x1f
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orr r0,r0,#0xd3
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msr cpsr,r0
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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bl cpu_init_crit
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#endif
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#ifdef CONFIG_CPU_PXA25X
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bl lock_cache_for_stack
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#endif
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#ifdef CONFIG_CPU_PXA27X
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/*
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* enable clock for SRAM
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*/
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ldr r0,=CKEN
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ldr r1,[r0]
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orr r1,r1,#(1 << 20)
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str r1,[r0]
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#endif
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bl _main
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/*------------------------------------------------------------------------------*/
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.globl c_runtime_cpu_setup
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c_runtime_cpu_setup:
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#ifdef CONFIG_CPU_PXA25X
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/*
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* Unlock (actually, disable) the cache now that board_init_f
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* is done. We could do this earlier but we would need to add
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* a new C runtime hook, whereas c_runtime_cpu_setup already
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* exists.
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* As this routine is just a call to cpu_init_crit, let us
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* tail-optimize and do a simple branch here.
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*/
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b cpu_init_crit
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#else
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bx lr
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#endif
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
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cpu_init_crit:
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/*
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* flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
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mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS)
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bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
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orr r0, r0, #0x00000002 @ set bit 1 (A) Align
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mcr p15, 0, r0, c1, c0, 0
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mov pc, lr /* back to my caller */
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#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */
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/*
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* Enable MMU to use DCache as DRAM.
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*
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* This is useful on PXA25x and PXA26x in early bootstages, where there is no
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* other possible memory available to hold stack.
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*/
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#ifdef CONFIG_CPU_PXA25X
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.macro CPWAIT reg
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mrc p15, 0, \reg, c2, c0, 0
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mov \reg, \reg
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sub pc, pc, #4
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.endm
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lock_cache_for_stack:
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/* Domain access -- enable for all CPs */
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ldr r0, =0x0000ffff
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mcr p15, 0, r0, c3, c0, 0
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/* Point TTBR to MMU table */
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ldr r0, =mmutable
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mcr p15, 0, r0, c2, c0, 0
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/* Kick in MMU, ICache, DCache, BTB */
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mrc p15, 0, r0, c1, c0, 0
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bic r0, #0x1b00
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bic r0, #0x0087
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orr r0, #0x1800
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orr r0, #0x0005
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mcr p15, 0, r0, c1, c0, 0
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CPWAIT r0
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/* Unlock Icache, Dcache */
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mcr p15, 0, r0, c9, c1, 1
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mcr p15, 0, r0, c9, c2, 1
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/* Flush Icache, Dcache, BTB */
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mcr p15, 0, r0, c7, c7, 0
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/* Unlock I-TLB, D-TLB */
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mcr p15, 0, r0, c10, c4, 1
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mcr p15, 0, r0, c10, c8, 1
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/* Flush TLB */
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mcr p15, 0, r0, c8, c7, 0
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/* Allocate 4096 bytes of Dcache as RAM */
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/* Drain pending loads and stores */
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mcr p15, 0, r0, c7, c10, 4
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mov r4, #0x00
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mov r5, #0x00
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mov r2, #0x01
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mcr p15, 0, r0, c9, c2, 0
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CPWAIT r0
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/* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
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mov r0, #128
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ldr r1, =0xfffff000
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alloc:
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mcr p15, 0, r1, c7, c2, 5
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/* Drain pending loads and stores */
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mcr p15, 0, r0, c7, c10, 4
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strd r4, [r1], #8
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strd r4, [r1], #8
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strd r4, [r1], #8
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strd r4, [r1], #8
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subs r0, #0x01
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bne alloc
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/* Drain pending loads and stores */
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mcr p15, 0, r0, c7, c10, 4
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mov r2, #0x00
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mcr p15, 0, r2, c9, c2, 0
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CPWAIT r0
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mov pc, lr
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.section .mmutable, "a"
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mmutable:
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.align 14
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/* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
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.set __base, 0
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.rept 0xfff
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.word (__base << 20) | 0xc12
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.set __base, __base + 1
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.endr
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/* 0xfff00000 : 1:1, cached mapping */
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.word (0xfff << 20) | 0x1c1e
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#endif /* CONFIG_CPU_PXA25X */
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