mirror of
https://github.com/AsahiLinux/u-boot
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65cc0e2a65
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
89 lines
2.4 KiB
C
89 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
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*
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* Authors: Nick.Spence@freescale.com
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* Wilson.Lo@freescale.com
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* scottwood@freescale.com
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*
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* This files is mostly identical to the original from
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* board\freescale\mpc8315erdb\sdram.c
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*/
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#ifndef CONFIG_MPC83XX_SDRAM
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#include <common.h>
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#include <init.h>
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#include <mpc83xx.h>
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#include <spd_sdram.h>
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#include <asm/bitops.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Fixed sdram init -- doesn't use serial presence detect.
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*
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* This is useful for faster booting in configs where the RAM is unlikely
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* to be changed, or for things like NAND booting where space is tight.
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*/
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static long fixed_sdram(void)
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = CFG_SYS_SDRAM_SIZE;
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u32 msize_log2 = __ilog2(msize);
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out_be32(&im->sysconf.ddrlaw[0].bar,
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CFG_SYS_SDRAM_BASE & 0xfffff000);
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out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
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out_be32(&im->sysconf.ddrcdr, CFG_SYS_DDRCDR_VALUE);
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out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
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out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG);
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/* Currently we use only one CS, so disable the other bank. */
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out_be32(&im->ddr.cs_config[1], 0);
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out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_SDRAM_CLK_CNTL);
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out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3);
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out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1);
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out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2);
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out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);
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out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG);
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out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2);
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out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE);
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out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2);
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out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL);
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sync();
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/* enable DDR controller */
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setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
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sync();
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return get_ram_size(CFG_SYS_SDRAM_BASE, msize);
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}
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int dram_init(void)
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize;
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if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
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return -ENXIO;
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/* DDR SDRAM */
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msize = fixed_sdram();
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/* return total bus SDRAM size(bytes) -- DDR */
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gd->ram_size = msize;
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return 0;
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}
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#endif /* !CONFIG_MPC83XX_SDRAM */
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