mirror of
https://github.com/AsahiLinux/u-boot
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cdc5ed8f1f
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NUM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
149 lines
3.8 KiB
C
149 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* Shengzhou Liu <Shengzhou.Liu@freescale.com>
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*/
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#include <common.h>
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#include <command.h>
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#include <fdt_support.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#include <malloc.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <fsl_dtsec.h>
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#include <asm/fsl_serdes.h>
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#include "../common/fman.h"
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int board_eth_init(struct bd_info *bis)
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{
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#if defined(CONFIG_FMAN_ENET)
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int i, interface;
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struct memac_mdio_info dtsec_mdio_info;
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struct memac_mdio_info tgec_mdio_info;
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struct mii_dev *dev;
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ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
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u32 srds_s1;
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srds_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
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srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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dtsec_mdio_info.regs =
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(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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/* Register the 1G MDIO bus */
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fm_memac_mdio_init(bis, &dtsec_mdio_info);
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tgec_mdio_info.regs =
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(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
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tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
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/* Register the 10G MDIO bus */
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fm_memac_mdio_init(bis, &tgec_mdio_info);
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/* Set the on-board RGMII PHY address */
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fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
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switch (srds_s1) {
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#ifdef CONFIG_TARGET_T1024RDB
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case 0x95:
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/* set the on-board RGMII2 PHY */
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fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
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/* set 10GBase-R with Aquantia AQR105 PHY */
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fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
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break;
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#endif
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case 0x6a:
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case 0x6b:
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case 0x77:
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case 0x135:
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/* set the on-board 2.5G SGMII AQR105 PHY */
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fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
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#ifdef CONFIG_TARGET_T1023RDB
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/* set the on-board 1G SGMII RTL8211F PHY */
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fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
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#endif
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break;
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default:
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printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
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srds_s1);
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break;
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}
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for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
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interface = fm_info_get_enet_if(i);
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switch (interface) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_ID:
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dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
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fm_info_set_mdio(i, dev);
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break;
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case PHY_INTERFACE_MODE_SGMII:
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#if defined(CONFIG_TARGET_T1023RDB)
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dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
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#elif defined(CONFIG_TARGET_T1024RDB)
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dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
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#endif
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fm_info_set_mdio(i, dev);
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break;
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case PHY_INTERFACE_MODE_2500BASEX:
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dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
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fm_info_set_mdio(i, dev);
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break;
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default:
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break;
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}
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}
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for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_XGMII:
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dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
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fm_info_set_mdio(i, dev);
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break;
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default:
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break;
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}
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}
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cpu_eth_init(bis);
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#endif /* CONFIG_FMAN_ENET */
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return pci_eth_init(bis);
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}
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void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
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enum fm_port port, int offset)
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{
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#if defined(CONFIG_TARGET_T1024RDB)
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if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) ||
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(fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
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(port == FM1_DTSEC3)) {
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fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
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fdt_setprop_string(fdt, offset, "phy-connection-type",
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"2500base-x");
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fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
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}
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#endif
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}
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void fdt_fixup_board_enet(void *fdt)
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{
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}
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