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5213d24d7b
The existing timing does not quite meet the minimum requirements in the LAN9221 datasheet. The timing in this patch solves problems noticed on some parts. The patch also combines the CS configuration for the overo and igep0020 boards per request. Signed-off-by: Philip Balister <philip@opensdr.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
92 lines
2.5 KiB
C
92 lines
2.5 KiB
C
/*
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* (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
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* Rohit Choraria <rohitkc@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_OMAP_GPMC_H
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#define __ASM_ARCH_OMAP_GPMC_H
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#define GPMC_BUF_EMPTY 0
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#define GPMC_BUF_FULL 1
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#define ECCCLEAR (0x1 << 8)
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#define ECCRESULTREG1 (0x1 << 0)
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#define ECCSIZE512BYTE 0xFF
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#define ECCSIZE1 (ECCSIZE512BYTE << 22)
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#define ECCSIZE0 (ECCSIZE512BYTE << 12)
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#define ECCSIZE0SEL (0x000 << 0)
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/* Generic ECC Layouts */
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/* Large Page x8 NAND device Layout */
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#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
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#define GPMC_NAND_HW_ECC_LAYOUT {\
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.eccbytes = 12,\
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.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
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9, 10, 11, 12},\
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.oobfree = {\
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{.offset = 13,\
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.length = 51 } } \
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}
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#endif
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/* Large Page x16 NAND device Layout */
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#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
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#define GPMC_NAND_HW_ECC_LAYOUT {\
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.eccbytes = 12,\
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.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13},\
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.oobfree = {\
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{.offset = 14,\
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.length = 50 } } \
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}
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#endif
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/* Small Page x8 NAND device Layout */
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#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
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#define GPMC_NAND_HW_ECC_LAYOUT {\
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.eccbytes = 3,\
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.eccpos = {1, 2, 3},\
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.oobfree = {\
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{.offset = 4,\
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.length = 12 } } \
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}
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#endif
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/* Small Page x16 NAND device Layout */
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#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
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#define GPMC_NAND_HW_ECC_LAYOUT {\
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.eccbytes = 3,\
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.eccpos = {2, 3, 4},\
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.oobfree = {\
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{.offset = 5,\
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.length = 11 } } \
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}
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#endif
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/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
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#define NET_LAN9221_GPMC_CONFIG1 0x00001000
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#define NET_LAN9221_GPMC_CONFIG2 0x00060700
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#define NET_LAN9221_GPMC_CONFIG3 0x00020201
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#define NET_LAN9221_GPMC_CONFIG4 0x06000700
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#define NET_LAN9221_GPMC_CONFIG5 0x0006090A
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#define NET_LAN9221_GPMC_CONFIG6 0x87030000
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#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
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#endif /* __ASM_ARCH_OMAP_GPMC_H */
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