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https://github.com/AsahiLinux/u-boot
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06b5301043
Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Updated MAINTAINERS files
Dropped #ifdef in cpu.h
Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
98 lines
2.9 KiB
C
98 lines
2.9 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __LS2_EMU_H
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#define __LS2_EMU_H
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#include "ls2080a_common.h"
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#ifdef CONFIG_LS2080A
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#define CONFIG_IDENT_STRING " LS2080A-EMU"
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#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-EMU"
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#endif
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#ifdef CONFIG_LS2085A
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#define CONFIG_IDENT_STRING " LS2085A-EMU"
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#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU"
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#endif
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#define CONFIG_SYS_CLK_FREQ 100000000
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#define CONFIG_DDR_CLK_FREQ 133333333
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#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
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#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
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#define CONFIG_DDR_SPD
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#define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */
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#define SPD_EEPROM_ADDRESS1 0x51
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#define SPD_EEPROM_ADDRESS2 0x52
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#define SPD_EEPROM_ADDRESS3 0x53
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#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
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#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 4
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
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#endif
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#define CONFIG_FSL_DDR_SYNC_REFRESH
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#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
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#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
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/*
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* NOR Flash Timing Params
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*/
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#define CONFIG_SYS_NOR0_CSPR \
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(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR0_CSPR_EARLY \
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(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
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#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
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FTIM0_NOR_TEADC(0x1) | \
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FTIM0_NOR_TEAHC(0x1))
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#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
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FTIM1_NOR_TRAD_NOR(0x1))
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#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
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FTIM2_NOR_TCH(0x0) | \
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FTIM2_NOR_TWP(0x1))
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#define CONFIG_SYS_NOR_FTIM3 0x04000000
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#define CONFIG_SYS_IFC_CCR 0x01000000
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
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#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
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/* Debug Server firmware */
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#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
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#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
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/*
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* This trick allows users to load MC images into DDR directly without
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* copying from NOR flash. It dramatically improves speed.
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*/
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#define CONFIG_SYS_LS_MC_FW_IN_DDR
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#define CONFIG_SYS_LS_MC_DPL_IN_DDR
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#define CONFIG_SYS_LS_MC_DPC_IN_DDR
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#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
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/* Store environment at top of flash */
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#define CONFIG_ENV_IS_NOWHERE 1
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#define CONFIG_ENV_SIZE 0x1000
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#endif /* __LS2_EMU_H */
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