mirror of
https://github.com/AsahiLinux/u-boot
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55171aedda
The original function was only called once, before relocation. The new
one is called again after relocation. This was not the intent of the
original call. Fix this by renaming and updating the calling logic.
With this, chromebook_link64 makes it through SPL.
Fixes: 7fe32b3442 ("event: Convert arch_cpu_init_dm() to use events")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
173 lines
3 KiB
C
173 lines
3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015
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* Purna Chandra Mandal <purna.mandal@microchip.com>
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*
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <event.h>
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#include <init.h>
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#include <malloc.h>
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#include <asm/global_data.h>
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#include <mach/pic32.h>
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#include <mach/ddr.h>
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#include <dt-bindings/clock/microchip,clock.h>
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/* Flash prefetch */
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#define PRECON 0x00
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/* Flash ECCCON */
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#define ECC_MASK 0x03
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#define ECC_SHIFT 4
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#define CLK_MHZ(x) ((x) / 1000000)
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DECLARE_GLOBAL_DATA_PTR;
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static ulong rate(int id)
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{
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int ret;
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struct udevice *dev;
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struct clk clk;
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ulong rate;
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ret = uclass_get_device(UCLASS_CLK, 0, &dev);
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if (ret) {
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printf("clk-uclass not found\n");
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return 0;
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}
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clk.id = id;
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ret = clk_request(dev, &clk);
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if (ret < 0)
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return ret;
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rate = clk_get_rate(&clk);
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clk_free(&clk);
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return rate;
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}
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static ulong clk_get_cpu_rate(void)
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{
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return rate(PB7CLK);
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}
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/* initialize prefetch module related to cpu_clk */
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static void prefetch_init(void)
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{
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struct pic32_reg_atomic *regs;
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const void __iomem *base;
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int v, nr_waits;
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ulong rate;
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/* cpu frequency in MHZ */
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rate = clk_get_cpu_rate() / 1000000;
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/* get flash ECC type */
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base = pic32_get_syscfg_base();
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v = (readl(base + CFGCON) >> ECC_SHIFT) & ECC_MASK;
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if (v < 2) {
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if (rate < 66)
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nr_waits = 0;
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else if (rate < 133)
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nr_waits = 1;
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else
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nr_waits = 2;
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} else {
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if (rate <= 83)
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nr_waits = 0;
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else if (rate <= 166)
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nr_waits = 1;
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else
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nr_waits = 2;
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}
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regs = ioremap(PREFETCH_BASE + PRECON, sizeof(*regs));
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writel(nr_waits, ®s->raw);
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/* Enable prefetch for all */
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writel(0x30, ®s->set);
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iounmap(regs);
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}
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/* arch specific CPU init after DM */
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static int pic32_flash_prefetch(void *ctx, struct event *event)
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{
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/* flash prefetch */
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prefetch_init();
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return 0;
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}
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EVENT_SPY(EVT_DM_POST_INIT_F, pic32_flash_prefetch);
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/* Un-gate DDR2 modules (gated by default) */
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static void ddr2_pmd_ungate(void)
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{
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void __iomem *regs;
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regs = pic32_get_syscfg_base();
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writel(0, regs + PMD7);
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}
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/* initialize the DDR2 Controller and DDR2 PHY */
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int dram_init(void)
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{
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ddr2_pmd_ungate();
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ddr2_phy_init();
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ddr2_ctrl_init();
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gd->ram_size = ddr2_calculate_size();
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return 0;
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}
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int misc_init_r(void)
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{
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set_io_port_base(0);
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return 0;
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}
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#ifdef CONFIG_DISPLAY_BOARDINFO
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const char *get_core_name(void)
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{
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u32 proc_id;
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const char *str;
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proc_id = read_c0_prid();
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switch (proc_id) {
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case 0x19e28:
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str = "PIC32MZ[DA]";
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break;
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default:
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str = "UNKNOWN";
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}
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return str;
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}
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#endif
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#ifdef CONFIG_CMD_CLK
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int soc_clk_dump(void)
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{
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int i;
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printf("PLL Speed: %lu MHz\n",
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CLK_MHZ(rate(PLLCLK)));
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printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK)));
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printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL)));
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for (i = PB1CLK; i <= PB7CLK; i++)
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printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1,
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CLK_MHZ(rate(i)));
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for (i = REF1CLK; i <= REF5CLK; i++)
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printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,
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CLK_MHZ(rate(i)));
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return 0;
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}
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#endif
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