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Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
304 lines
8.4 KiB
C
304 lines
8.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#ifndef __CVMX_QLM_H__
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#define __CVMX_QLM_H__
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/*
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* Interface 0 on the 78xx can be connected to qlm 0 or qlm 2. When interface
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* 0 is connected to qlm 0, this macro must be set to 0. When interface 0 is
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* connected to qlm 2, this macro must be set to 1.
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*/
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#define MUX_78XX_IFACE0 0
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/*
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* Interface 1 on the 78xx can be connected to qlm 1 or qlm 3. When interface
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* 1 is connected to qlm 1, this macro must be set to 0. When interface 1 is
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* connected to qlm 3, this macro must be set to 1.
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*/
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#define MUX_78XX_IFACE1 0
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/* Uncomment this line to print QLM JTAG state */
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/* #define CVMX_QLM_DUMP_STATE 1 */
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typedef struct {
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const char *name;
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int stop_bit;
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int start_bit;
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} __cvmx_qlm_jtag_field_t;
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/**
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* Return the number of QLMs supported by the chip
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*
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* Return: Number of QLMs
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*/
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int cvmx_qlm_get_num(void);
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/**
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* Return the qlm number based on the interface
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*
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* @param xiface Interface to look
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*/
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int cvmx_qlm_interface(int xiface);
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/**
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* Return the qlm number based for a port in the interface
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*
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* @param xiface interface to look up
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* @param index index in an interface
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*
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* Return: the qlm number based on the xiface
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*/
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int cvmx_qlm_lmac(int xiface, int index);
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/**
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* Return if only DLM5/DLM6/DLM5+DLM6 is used by BGX
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*
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* @param BGX BGX to search for.
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*
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* Return: muxes used 0 = DLM5+DLM6, 1 = DLM5, 2 = DLM6.
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*/
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int cvmx_qlm_mux_interface(int bgx);
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/**
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* Return number of lanes for a given qlm
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*
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* @param qlm QLM block to query
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*
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* Return: Number of lanes
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*/
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int cvmx_qlm_get_lanes(int qlm);
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/**
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* Get the QLM JTAG fields based on Octeon model on the supported chips.
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*
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* Return: qlm_jtag_field_t structure
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*/
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const __cvmx_qlm_jtag_field_t *cvmx_qlm_jtag_get_field(void);
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/**
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* Get the QLM JTAG length by going through qlm_jtag_field for each
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* Octeon model that is supported
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*
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* Return: return the length.
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*/
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int cvmx_qlm_jtag_get_length(void);
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/**
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* Initialize the QLM layer
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*/
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void cvmx_qlm_init(void);
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/**
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* Get a field in a QLM JTAG chain
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*
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* @param qlm QLM to get
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* @param lane Lane in QLM to get
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* @param name String name of field
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*
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* Return: JTAG field value
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*/
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u64 cvmx_qlm_jtag_get(int qlm, int lane, const char *name);
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/**
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* Set a field in a QLM JTAG chain
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*
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* @param qlm QLM to set
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* @param lane Lane in QLM to set, or -1 for all lanes
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* @param name String name of field
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* @param value Value of the field
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*/
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void cvmx_qlm_jtag_set(int qlm, int lane, const char *name, u64 value);
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/**
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* Errata G-16094: QLM Gen2 Equalizer Default Setting Change.
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* CN68XX pass 1.x and CN66XX pass 1.x QLM tweak. This function tweaks the
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* JTAG setting for a QLMs to run better at 5 and 6.25Ghz.
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*/
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void __cvmx_qlm_speed_tweak(void);
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/**
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* Errata G-16174: QLM Gen2 PCIe IDLE DAC change.
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* CN68XX pass 1.x, CN66XX pass 1.x and CN63XX pass 1.0-2.2 QLM tweak.
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* This function tweaks the JTAG setting for a QLMs for PCIe to run better.
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*/
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void __cvmx_qlm_pcie_idle_dac_tweak(void);
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void __cvmx_qlm_pcie_cfg_rxd_set_tweak(int qlm, int lane);
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/**
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* Get the speed (Gbaud) of the QLM in Mhz.
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*
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* @param qlm QLM to examine
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*
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* Return: Speed in Mhz
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*/
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int cvmx_qlm_get_gbaud_mhz(int qlm);
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/**
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* Get the speed (Gbaud) of the QLM in Mhz on specific node.
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*
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* @param node Target QLM node
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* @param qlm QLM to examine
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*
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* Return: Speed in Mhz
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*/
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int cvmx_qlm_get_gbaud_mhz_node(int node, int qlm);
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enum cvmx_qlm_mode {
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CVMX_QLM_MODE_DISABLED = -1,
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CVMX_QLM_MODE_SGMII = 1,
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CVMX_QLM_MODE_XAUI,
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CVMX_QLM_MODE_RXAUI,
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CVMX_QLM_MODE_PCIE, /* gen3 / gen2 / gen1 */
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CVMX_QLM_MODE_PCIE_1X2, /* 1x2 gen2 / gen1 */
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CVMX_QLM_MODE_PCIE_2X1, /* 2x1 gen2 / gen1 */
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CVMX_QLM_MODE_PCIE_1X1, /* 1x1 gen2 / gen1 */
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CVMX_QLM_MODE_SRIO_1X4, /* 1x4 short / long */
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CVMX_QLM_MODE_SRIO_2X2, /* 2x2 short / long */
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CVMX_QLM_MODE_SRIO_4X1, /* 4x1 short / long */
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CVMX_QLM_MODE_ILK,
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CVMX_QLM_MODE_QSGMII,
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CVMX_QLM_MODE_SGMII_SGMII,
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CVMX_QLM_MODE_SGMII_DISABLED,
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CVMX_QLM_MODE_DISABLED_SGMII,
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CVMX_QLM_MODE_SGMII_QSGMII,
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CVMX_QLM_MODE_QSGMII_QSGMII,
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CVMX_QLM_MODE_QSGMII_DISABLED,
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CVMX_QLM_MODE_DISABLED_QSGMII,
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CVMX_QLM_MODE_QSGMII_SGMII,
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CVMX_QLM_MODE_RXAUI_1X2,
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CVMX_QLM_MODE_SATA_2X1,
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CVMX_QLM_MODE_XLAUI,
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CVMX_QLM_MODE_XFI,
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CVMX_QLM_MODE_10G_KR,
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CVMX_QLM_MODE_40G_KR4,
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CVMX_QLM_MODE_PCIE_1X8, /* 1x8 gen3 / gen2 / gen1 */
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CVMX_QLM_MODE_RGMII_SGMII,
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CVMX_QLM_MODE_RGMII_XFI,
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CVMX_QLM_MODE_RGMII_10G_KR,
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CVMX_QLM_MODE_RGMII_RXAUI,
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CVMX_QLM_MODE_RGMII_XAUI,
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CVMX_QLM_MODE_RGMII_XLAUI,
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CVMX_QLM_MODE_RGMII_40G_KR4,
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CVMX_QLM_MODE_MIXED, /* BGX2 is mixed mode, DLM5(SGMII) & DLM6(XFI) */
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CVMX_QLM_MODE_SGMII_2X1, /* Configure BGX2 separate for DLM5 & DLM6 */
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CVMX_QLM_MODE_10G_KR_1X2, /* Configure BGX2 separate for DLM5 & DLM6 */
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CVMX_QLM_MODE_XFI_1X2, /* Configure BGX2 separate for DLM5 & DLM6 */
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CVMX_QLM_MODE_RGMII_SGMII_1X1, /* Configure BGX2, applies to DLM5 */
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CVMX_QLM_MODE_RGMII_SGMII_2X1, /* Configure BGX2, applies to DLM6 */
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CVMX_QLM_MODE_RGMII_10G_KR_1X1, /* Configure BGX2, applies to DLM6 */
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CVMX_QLM_MODE_RGMII_XFI_1X1, /* Configure BGX2, applies to DLM6 */
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CVMX_QLM_MODE_SDL, /* RMAC Pipe */
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CVMX_QLM_MODE_CPRI, /* RMAC */
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CVMX_QLM_MODE_OCI
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};
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enum cvmx_gmx_inf_mode {
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CVMX_GMX_INF_MODE_DISABLED = 0,
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CVMX_GMX_INF_MODE_SGMII = 1, /* Other interface can be SGMII or QSGMII */
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CVMX_GMX_INF_MODE_QSGMII = 2, /* Other interface can be SGMII or QSGMII */
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CVMX_GMX_INF_MODE_RXAUI = 3, /* Only interface 0, interface 1 must be DISABLED */
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};
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/**
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* Eye diagram captures are stored in the following structure
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*/
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typedef struct {
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int width; /* Width in the x direction (time) */
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int height; /* Height in the y direction (voltage) */
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u32 data[64][128]; /* Error count at location, saturates as max */
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} cvmx_qlm_eye_t;
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/**
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* These apply to DLM1 and DLM2 if its not in SATA mode
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* Manual refers to lanes as follows:
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* DML 0 lane 0 == GSER0 lane 0
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* DML 0 lane 1 == GSER0 lane 1
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* DML 1 lane 2 == GSER1 lane 0
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* DML 1 lane 3 == GSER1 lane 1
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* DML 2 lane 4 == GSER2 lane 0
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* DML 2 lane 5 == GSER2 lane 1
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*/
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enum cvmx_pemx_cfg_mode {
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CVMX_PEM_MD_GEN2_2LANE = 0, /* Valid for PEM0(DLM1), PEM1(DLM2) */
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CVMX_PEM_MD_GEN2_1LANE = 1, /* Valid for PEM0(DLM1.0), PEM1(DLM1.1,DLM2.0), PEM2(DLM2.1) */
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CVMX_PEM_MD_GEN2_4LANE = 2, /* Valid for PEM0(DLM1-2) */
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/* Reserved */
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CVMX_PEM_MD_GEN1_2LANE = 4, /* Valid for PEM0(DLM1), PEM1(DLM2) */
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CVMX_PEM_MD_GEN1_1LANE = 5, /* Valid for PEM0(DLM1.0), PEM1(DLM1.1,DLM2.0), PEM2(DLM2.1) */
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CVMX_PEM_MD_GEN1_4LANE = 6, /* Valid for PEM0(DLM1-2) */
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/* Reserved */
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};
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/*
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* Read QLM and return mode.
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*/
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enum cvmx_qlm_mode cvmx_qlm_get_mode(int qlm);
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enum cvmx_qlm_mode cvmx_qlm_get_mode_cn78xx(int node, int qlm);
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enum cvmx_qlm_mode cvmx_qlm_get_dlm_mode(int dlm_mode, int interface);
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void __cvmx_qlm_set_mult(int qlm, int baud_mhz, int old_multiplier);
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void cvmx_qlm_display_registers(int qlm);
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int cvmx_qlm_measure_clock(int qlm);
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/**
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* Measure the reference clock of a QLM on a multi-node setup
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*
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* @param node node to measure
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* @param qlm QLM to measure
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*
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* Return: Clock rate in Hz
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*/
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int cvmx_qlm_measure_clock_node(int node, int qlm);
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/*
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* Perform RX equalization on a QLM
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*
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* @param node Node the QLM is on
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* @param qlm QLM to perform RX equalization on
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* @param lane Lane to use, or -1 for all lanes
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*
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* Return: Zero on success, negative if any lane failed RX equalization
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*/
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int __cvmx_qlm_rx_equalization(int node, int qlm, int lane);
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/**
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* Errata GSER-27882 -GSER 10GBASE-KR Transmit Equalizer
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* Training may not update PHY Tx Taps. This function is not static
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* so we can share it with BGX KR
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*
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* @param node Node to apply errata workaround
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* @param qlm QLM to apply errata workaround
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* @param lane Lane to apply the errata
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*/
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int cvmx_qlm_gser_errata_27882(int node, int qlm, int lane);
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void cvmx_qlm_gser_errata_25992(int node, int qlm);
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#ifdef CVMX_DUMP_GSER
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/**
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* Dump GSER configuration for node 0
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*/
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int cvmx_dump_gser_config(unsigned int gser);
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/**
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* Dump GSER status for node 0
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*/
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int cvmx_dump_gser_status(unsigned int gser);
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/**
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* Dump GSER configuration
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*/
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int cvmx_dump_gser_config_node(unsigned int node, unsigned int gser);
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/**
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* Dump GSER status
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*/
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int cvmx_dump_gser_status_node(unsigned int node, unsigned int gser);
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#endif
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int cvmx_qlm_eye_display(int node, int qlm, int qlm_lane, int format, const cvmx_qlm_eye_t *eye);
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void cvmx_prbs_process_cmd(int node, int qlm, int mode);
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#endif /* __CVMX_QLM_H__ */
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