mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-22 11:13:07 +00:00
739ba41d5a
The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
34 lines
843 B
C
34 lines
843 B
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2015-2017 Socionext Inc.
|
|
*/
|
|
|
|
#include <linux/io.h>
|
|
|
|
#include "../init.h"
|
|
#include "../sc-regs.h"
|
|
|
|
void uniphier_pro5_dram_clk_init(void)
|
|
{
|
|
u32 tmp;
|
|
|
|
/*
|
|
* deassert reset
|
|
* UMCA2: Ch1 (DDR3)
|
|
* UMCA1, UMC31: Ch0 (WIO1)
|
|
* UMCA0, UMC30: Ch0 (WIO0)
|
|
*/
|
|
tmp = readl(sc_base + SC_RSTCTRL4);
|
|
tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
|
|
SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
|
|
SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30;
|
|
writel(tmp, sc_base + SC_RSTCTRL4);
|
|
readl(sc_base + SC_RSTCTRL4); /* dummy read */
|
|
|
|
/* provide clocks */
|
|
tmp = readl(sc_base + SC_CLKCTRL4);
|
|
tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 |
|
|
SC_CLKCTRL4_CEN_UMC0;
|
|
writel(tmp, sc_base + SC_CLKCTRL4);
|
|
readl(sc_base + SC_CLKCTRL4); /* dummy read */
|
|
}
|