mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-21 18:53:06 +00:00
0b42fdca2d
Synchronise device tree with linux v6.1-rc3.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8m{m,n,p}-venice-*
175 lines
3.8 KiB
Text
175 lines
3.8 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 NXP
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* Copyright (c) 2019 Engicam srl
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* Copyright (c) 2020 Amarula Solutions(India)
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*/
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/dts-v1/;
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#include "imx8mp.dtsi"
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#include "imx8mp-icore-mx8mp.dtsi"
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#include <dt-bindings/usb/pd.h>
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/ {
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model = "Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit";
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compatible = "engicam,icore-mx8mp-edimm2.2", "engicam,icore-mx8mp",
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"fsl,imx8mp";
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chosen {
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stdout-path = &uart2;
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};
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reg_usb1_vbus: regulator-usb1 {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usb1>;
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regulator-max-microvolt = <5000000>;
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regulator-min-microvolt = <5000000>;
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regulator-name = "usb1_host_vbus";
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "VSD_3V3";
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};
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};
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/* Ethernet */
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&eqos {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos>;
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phy-handle = <ðphy0>;
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phy-mode = "rgmii-id";
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@7 {
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compatible = "ethernet-phy-ieee802.3-c22";
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micrel,led-mode = <0>;
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reg = <7>;
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};
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};
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};
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/* console */
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&usb3_phy0 {
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status = "okay";
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};
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&usb3_0 {
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status = "okay";
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};
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&usb_dwc3_0 {
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dr_mode = "host";
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status = "okay";
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};
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&usb3_phy1 {
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status = "okay";
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};
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&usb3_1 {
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status = "okay";
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};
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&usb_dwc3_1 {
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dr_mode = "host";
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status = "okay";
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};
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/* SDCARD */
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&usdhc2 {
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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pinctrl-names = "default" ;
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
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MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
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MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
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MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
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MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
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MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
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MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
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MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
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MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
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MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
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MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
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MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
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MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
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MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
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MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x10
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40
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MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
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MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
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MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x140
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
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MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
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MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2gpiogrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
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>;
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};
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pinctrl_reg_usb1: regusb1grp {
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fsl,pins = <
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MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x10
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
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>;
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};
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};
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