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u-boot/board/sunxi/Kconfig
Chen-Yu Tsai 409677ec17 sunxi: Enable AXP221s in I2C mode with the R40 SoC 
The R40 SoC uses the AXP221s in I2C mode to supply power.

Some regulator's common usages have changed, and also the recommended
voltage for existing usages have changed. Update the defaults to match.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:30:00 +02:00

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if ARCH_SUNXI
config IDENT_STRING
default " Allwinner Technology"
# FIXME: Should not redefine these Kconfig symbols
config PRE_CONSOLE_BUFFER
default y
config SPL_GPIO_SUPPORT
default y
config SPL_LIBCOMMON_SUPPORT
default y
config SPL_LIBDISK_SUPPORT
default y
config SPL_LIBGENERIC_SUPPORT
default y
config SPL_MMC_SUPPORT
depends on SPL && GENERIC_MMC
default y
config SPL_POWER_SUPPORT
default y
config SPL_SERIAL_SUPPORT
default y
config SUNXI_HIGH_SRAM
bool
default n
---help---
Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
with the first SRAM region being located at address 0.
Some newer SoCs map the boot ROM at address 0 instead and move the
SRAM to 64KB, just behind the mask ROM.
Chips using the latter setup are supposed to select this option to
adjust the addresses accordingly.
# Note only one of these may be selected at a time! But hidden choices are
# not supported by Kconfig
config SUNXI_GEN_SUN4I
bool
---help---
Select this for sunxi SoCs which have resets and clocks set up
as the original A10 (mach-sun4i).
config SUNXI_GEN_SUN6I
bool
---help---
Select this for sunxi SoCs which have sun6i like periphery, like
separate ahb reset control registers, custom pmic bus, new style
watchdog, etc.
config MACH_SUNXI_H3_H5
bool
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
choice
prompt "Sunxi SoC Variant"
optional
config MACH_SUN4I
bool "sun4i (Allwinner A10)"
select CPU_V7
select ARM_CORTEX_CPU_IS_UP
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
config MACH_SUN5I
bool "sun5i (Allwinner A13)"
select CPU_V7
select ARM_CORTEX_CPU_IS_UP
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
config MACH_SUN6I
bool "sun6i (Allwinner A31)"
select CPU_V7
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
config MACH_SUN7I
bool "sun7i (Allwinner A20)"
select CPU_V7
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
config MACH_SUN8I_A23
bool "sun8i (Allwinner A23)"
select CPU_V7
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
config MACH_SUN8I_A33
bool "sun8i (Allwinner A33)"
select CPU_V7
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
config MACH_SUN8I_A83T
bool "sun8i (Allwinner A83T)"
select CPU_V7
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
config MACH_SUN8I_H3
bool "sun8i (Allwinner H3)"
select CPU_V7
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
select MACH_SUNXI_H3_H5
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
config MACH_SUN8I_R40
bool "sun8i (Allwinner R40)"
select CPU_V7
select SUNXI_GEN_SUN6I
config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7
select SUNXI_HIGH_SRAM
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
config MACH_SUN50I
bool "sun50i (Allwinner A64)"
select ARM64
select SUNXI_GEN_SUN6I
select SUNXI_HIGH_SRAM
select SUPPORT_SPL
config MACH_SUN50I_H5
bool "sun50i (Allwinner H5)"
select ARM64
select MACH_SUNXI_H3_H5
select SUNXI_HIGH_SRAM
endchoice
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
config MACH_SUN8I
bool
default y if MACH_SUN8I_A23
default y if MACH_SUN8I_A33
default y if MACH_SUN8I_A83T
default y if MACH_SUNXI_H3_H5
default y if MACH_SUN8I_R40
config RESERVE_ALLWINNER_BOOT0_HEADER
bool "reserve space for Allwinner boot0 header"
select ENABLE_ARM_SOC_BOOT0_HOOK
---help---
Prepend a 1536 byte (empty) header to the U-Boot image file, to be
filled with magic values post build. The Allwinner provided boot0
blob relies on this information to load and execute U-Boot.
Only needed on 64-bit Allwinner boards so far when using boot0.
config ARM_BOOT_HOOK_RMR
bool
depends on ARM64
default y
select ENABLE_ARM_SOC_BOOT0_HOOK
---help---
Insert some ARM32 code at the very beginning of the U-Boot binary
which uses an RMR register write to bring the core into AArch64 mode.
The very first instruction acts as a switch, since it's carefully
chosen to be a NOP in one mode and a branch in the other, so the
code would only be executed if not already in AArch64.
This allows both the SPL and the U-Boot proper to be entered in
either mode and switch to AArch64 if needed.
config DRAM_TYPE
int "sunxi dram type"
depends on MACH_SUN8I_A83T
default 3
---help---
Set the dram type, 3: DDR3, 7: LPDDR3
config DRAM_CLK
int "sunxi dram clock speed"
default 792 if MACH_SUN9I
default 312 if MACH_SUN6I || MACH_SUN8I
default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
default 672 if MACH_SUN50I
---help---
Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
must be a multiple of 24. For the sun9i (A80), the tested values
(for DDR3-1600) are 312 to 792.
if MACH_SUN5I || MACH_SUN7I
config DRAM_MBUS_CLK
int "sunxi mbus clock speed"
default 300
---help---
Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
endif
config DRAM_ZQ
int "sunxi dram zq value"
default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
default 127 if MACH_SUN7I
default 4145117 if MACH_SUN9I
default 3881915 if MACH_SUN50I
---help---
Set the dram zq value.
config DRAM_ODT_EN
bool "sunxi dram odt enable"
default n if !MACH_SUN8I_A23
default y if MACH_SUN8I_A23
default y if MACH_SUN50I
---help---
Select this to enable dram odt (on die termination).
if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
config DRAM_EMR1
int "sunxi dram emr1 value"
default 0 if MACH_SUN4I
default 4 if MACH_SUN5I || MACH_SUN7I
---help---
Set the dram controller emr1 value.
config DRAM_TPR3
hex "sunxi dram tpr3 value"
default 0
---help---
Set the dram controller tpr3 parameter. This parameter configures
the delay on the command lane and also phase shifts, which are
applied for sampling incoming read data. The default value 0
means that no phase/delay adjustments are necessary. Properly
configuring this parameter increases reliability at high DRAM
clock speeds.
config DRAM_DQS_GATING_DELAY
hex "sunxi dram dqs_gating_delay value"
default 0
---help---
Set the dram controller dqs_gating_delay parmeter. Each byte
encodes the DQS gating delay for each byte lane. The delay
granularity is 1/4 cycle. For example, the value 0x05060606
means that the delay is 5 quarter-cycles for one lane (1.25
cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
The default value 0 means autodetection. The results of hardware
autodetection are not very reliable and depend on the chip
temperature (sometimes producing different results on cold start
and warm reboot). But the accuracy of hardware autodetection
is usually good enough, unless running at really high DRAM
clocks speeds (up to 600MHz). If unsure, keep as 0.
choice
prompt "sunxi dram timings"
default DRAM_TIMINGS_VENDOR_MAGIC
---help---
Select the timings of the DDR3 chips.
config DRAM_TIMINGS_VENDOR_MAGIC
bool "Magic vendor timings from Android"
---help---
The same DRAM timings as in the Allwinner boot0 bootloader.
config DRAM_TIMINGS_DDR3_1066F_1333H
bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
---help---
Use the timings of the standard JEDEC DDR3-1066F speed bin for
DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
that down binning to DDR3-1066F is supported (because DDR3-1066F
uses a bit faster timings than DDR3-1333H).
config DRAM_TIMINGS_DDR3_800E_1066G_1333J
bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
---help---
Use the timings of the slowest possible JEDEC speed bin for the
selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
DDR3-800E, DDR3-1066G or DDR3-1333J.
endchoice
endif
if MACH_SUN8I_A23
config DRAM_ODT_CORRECTION
int "sunxi dram odt correction value"
default 0
---help---
Set the dram odt correction value (range -255 - 255). In allwinner
fex files, this option is found in bits 8-15 of the u32 odt_en variable
in the [dram] section. When bit 31 of the odt_en variable is set
then the correction is negative. Usually the value for this is 0.
endif
config SYS_CLK_FREQ
default 1008000000 if MACH_SUN4I
default 1008000000 if MACH_SUN5I
default 1008000000 if MACH_SUN6I
default 912000000 if MACH_SUN7I
default 1008000000 if MACH_SUN8I
default 1008000000 if MACH_SUN9I
default 816000000 if MACH_SUN50I
config SYS_CONFIG_NAME
default "sun4i" if MACH_SUN4I
default "sun5i" if MACH_SUN5I
default "sun6i" if MACH_SUN6I
default "sun7i" if MACH_SUN7I
default "sun8i" if MACH_SUN8I
default "sun9i" if MACH_SUN9I
default "sun50i" if MACH_SUN50I
config SYS_BOARD
default "sunxi"
config SYS_SOC
default "sunxi"
config UART0_PORT_F
bool "UART0 on MicroSD breakout board"
default n
---help---
Repurpose the SD card slot for getting access to the UART0 serial
console. Primarily useful only for low level u-boot debugging on
tablets, where normal UART0 is difficult to access and requires
device disassembly and/or soldering. As the SD card can't be used
at the same time, the system can be only booted in the FEL mode.
Only enable this if you really know what you are doing.
config OLD_SUNXI_KERNEL_COMPAT
bool "Enable workarounds for booting old kernels"
default n
---help---
Set this to enable various workarounds for old kernels, this results in
sub-optimal settings for newer kernels, only enable if needed.
config MACPWR
string "MAC power pin"
default ""
help
Set the pin used to power the MAC. This takes a string in the format
understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
config MMC0_CD_PIN
string "Card detect pin for mmc0"
default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
default ""
---help---
Set the card detect pin for mmc0, leave empty to not use cd. This
takes a string in the format understood by sunxi_name_to_gpio, e.g.
PH1 for pin 1 of port H.
config MMC1_CD_PIN
string "Card detect pin for mmc1"
default ""
---help---
See MMC0_CD_PIN help text.
config MMC2_CD_PIN
string "Card detect pin for mmc2"
default ""
---help---
See MMC0_CD_PIN help text.
config MMC3_CD_PIN
string "Card detect pin for mmc3"
default ""
---help---
See MMC0_CD_PIN help text.
config MMC1_PINS
string "Pins for mmc1"
default ""
---help---
Set the pins used for mmc1, when applicable. This takes a string in the
format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
config MMC2_PINS
string "Pins for mmc2"
default ""
---help---
See MMC1_PINS help text.
config MMC3_PINS
string "Pins for mmc3"
default ""
---help---
See MMC1_PINS help text.
config MMC_SUNXI_SLOT_EXTRA
int "mmc extra slot number"
default -1
---help---
sunxi builds always enable mmc0, some boards also have a second sdcard
slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
support for this.
config INITIAL_USB_SCAN_DELAY
int "delay initial usb scan by x ms to allow builtin devices to init"
default 0
---help---
Some boards have on board usb devices which need longer than the
USB spec's 1 second to connect from board powerup. Set this config
option to a non 0 value to add an extra delay before the first usb
bus scan.
config USB0_VBUS_PIN
string "Vbus enable pin for usb0 (otg)"
default ""
---help---
Set the Vbus enable pin for usb0 (otg). This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
config USB0_VBUS_DET
string "Vbus detect pin for usb0 (otg)"
default ""
---help---
Set the Vbus detect pin for usb0 (otg). This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
config USB0_ID_DET
string "ID detect pin for usb0 (otg)"
default ""
---help---
Set the ID detect pin for usb0 (otg). This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
config USB1_VBUS_PIN
string "Vbus enable pin for usb1 (ehci0)"
default "PH6" if MACH_SUN4I || MACH_SUN7I
default "PH27" if MACH_SUN6I
---help---
Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
a string in the format understood by sunxi_name_to_gpio, e.g.
PH1 for pin 1 of port H.
config USB2_VBUS_PIN
string "Vbus enable pin for usb2 (ehci1)"
default "PH3" if MACH_SUN4I || MACH_SUN7I
default "PH24" if MACH_SUN6I
---help---
See USB1_VBUS_PIN help text.
config USB3_VBUS_PIN
string "Vbus enable pin for usb3 (ehci2)"
default ""
---help---
See USB1_VBUS_PIN help text.
config I2C0_ENABLE
bool "Enable I2C/TWI controller 0"
default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
default n if MACH_SUN6I || MACH_SUN8I
select CMD_I2C
---help---
This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
its clock and setting up the bus. This is especially useful on devices
with slaves connected to the bus or with pins exposed through e.g. an
expansion port/header.
config I2C1_ENABLE
bool "Enable I2C/TWI controller 1"
default n
select CMD_I2C
---help---
See I2C0_ENABLE help text.
config I2C2_ENABLE
bool "Enable I2C/TWI controller 2"
default n
select CMD_I2C
---help---
See I2C0_ENABLE help text.
if MACH_SUN6I || MACH_SUN7I
config I2C3_ENABLE
bool "Enable I2C/TWI controller 3"
default n
select CMD_I2C
---help---
See I2C0_ENABLE help text.
endif
if SUNXI_GEN_SUN6I
config R_I2C_ENABLE
bool "Enable the PRCM I2C/TWI controller"
# This is used for the pmic on H3
default y if SY8106A_POWER
select CMD_I2C
---help---
Set this to y to enable the I2C controller which is part of the PRCM.
endif
if MACH_SUN7I
config I2C4_ENABLE
bool "Enable I2C/TWI controller 4"
default n
select CMD_I2C
---help---
See I2C0_ENABLE help text.
endif
config AXP_GPIO
bool "Enable support for gpio-s on axp PMICs"
default n
---help---
Say Y here to enable support for the gpio pins of the axp PMIC ICs.
config VIDEO
bool "Enable graphical uboot console on HDMI, LCD or VGA"
depends on !MACH_SUN8I_A83T
depends on !MACH_SUNXI_H3_H5
depends on !MACH_SUN8I_R40
depends on !MACH_SUN9I
depends on !MACH_SUN50I
default y
---help---
Say Y here to add support for using a cfb console on the HDMI, LCD
or VGA output found on most sunxi devices. See doc/README.video for
info on how to select the video output and mode.
config VIDEO_HDMI
bool "HDMI output support"
depends on VIDEO && !MACH_SUN8I
default y
---help---
Say Y here to add support for outputting video over HDMI.
config VIDEO_VGA
bool "VGA output support"
depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
default n
---help---
Say Y here to add support for outputting video over VGA.
config VIDEO_VGA_VIA_LCD
bool "VGA via LCD controller support"
depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
default n
---help---
Say Y here to add support for external DACs connected to the parallel
LCD interface driving a VGA connector, such as found on the
Olimex A13 boards.
config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
bool "Force sync active high for VGA via LCD controller support"
depends on VIDEO_VGA_VIA_LCD
default n
---help---
Say Y here if you've a board which uses opendrain drivers for the vga
hsync and vsync signals. Opendrain drivers cannot generate steep enough
positive edges for a stable video output, so on boards with opendrain
drivers the sync signals must always be active high.
config VIDEO_VGA_EXTERNAL_DAC_EN
string "LCD panel power enable pin"
depends on VIDEO_VGA_VIA_LCD
default ""
---help---
Set the enable pin for the external VGA DAC. This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
config VIDEO_COMPOSITE
bool "Composite video output support"
depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
default n
---help---
Say Y here to add support for outputting composite video.
config VIDEO_LCD_MODE
string "LCD panel timing details"
depends on VIDEO
default ""
---help---
LCD panel timing details string, leave empty if there is no LCD panel.
This is in drivers/video/videomodes.c: video_get_params() format, e.g.
x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Also see: http://linux-sunxi.org/LCD
config VIDEO_LCD_DCLK_PHASE
int "LCD panel display clock phase"
depends on VIDEO
default 1
---help---
Select LCD panel display clock phase shift, range 0-3.
config VIDEO_LCD_POWER
string "LCD panel power enable pin"
depends on VIDEO
default ""
---help---
Set the power enable pin for the LCD panel. This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
config VIDEO_LCD_RESET
string "LCD panel reset pin"
depends on VIDEO
default ""
---help---
Set the reset pin for the LCD panel. This takes a string in the format
understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
config VIDEO_LCD_BL_EN
string "LCD panel backlight enable pin"
depends on VIDEO
default ""
---help---
Set the backlight enable pin for the LCD panel. This takes a string in the
the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
port H.
config VIDEO_LCD_BL_PWM
string "LCD panel backlight pwm pin"
depends on VIDEO
default ""
---help---
Set the backlight pwm pin for the LCD panel. This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
config VIDEO_LCD_BL_PWM_ACTIVE_LOW
bool "LCD panel backlight pwm is inverted"
depends on VIDEO
default y
---help---
Set this if the backlight pwm output is active low.
config VIDEO_LCD_PANEL_I2C
bool "LCD panel needs to be configured via i2c"
depends on VIDEO
default n
select CMD_I2C
---help---
Say y here if the LCD panel needs to be configured via i2c. This
will add a bitbang i2c controller using gpios to talk to the LCD.
config VIDEO_LCD_PANEL_I2C_SDA
string "LCD panel i2c interface SDA pin"
depends on VIDEO_LCD_PANEL_I2C
default "PG12"
---help---
Set the SDA pin for the LCD i2c interface. This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
config VIDEO_LCD_PANEL_I2C_SCL
string "LCD panel i2c interface SCL pin"
depends on VIDEO_LCD_PANEL_I2C
default "PG10"
---help---
Set the SCL pin for the LCD i2c interface. This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
# Note only one of these may be selected at a time! But hidden choices are
# not supported by Kconfig
config VIDEO_LCD_IF_PARALLEL
bool
config VIDEO_LCD_IF_LVDS
bool
choice
prompt "LCD panel support"
depends on VIDEO
---help---
Select which type of LCD panel to support.
config VIDEO_LCD_PANEL_PARALLEL
bool "Generic parallel interface LCD panel"
select VIDEO_LCD_IF_PARALLEL
config VIDEO_LCD_PANEL_LVDS
bool "Generic lvds interface LCD panel"
select VIDEO_LCD_IF_LVDS
config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
select VIDEO_LCD_SSD2828
select VIDEO_LCD_IF_PARALLEL
---help---
7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
select VIDEO_LCD_ANX9804
select VIDEO_LCD_IF_PARALLEL
select VIDEO_LCD_PANEL_I2C
---help---
Select this for eDP LCD panels with 4 lanes running at 1.62G,
connected via an ANX9804 bridge chip.
config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
bool "Hitachi tx18d42vm LCD panel"
select VIDEO_LCD_HITACHI_TX18D42VM
select VIDEO_LCD_IF_LVDS
---help---
7.85" 1024x768 Hitachi tx18d42vm LCD panel support
config VIDEO_LCD_TL059WV5C0
bool "tl059wv5c0 LCD panel"
select VIDEO_LCD_PANEL_I2C
select VIDEO_LCD_IF_PARALLEL
---help---
6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
Aigo M60/M608/M606 tablets.
endchoice
config SATAPWR
string "SATA power pin"
default ""
help
Set the pins used to power the SATA. This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
port H.
config GMAC_TX_DELAY
int "GMAC Transmit Clock Delay Chain"
default 0
---help---
Set the GMAC Transmit Clock Delay Chain value.
config SPL_STACK_R_ADDR
default 0x4fe00000 if MACH_SUN4I
default 0x4fe00000 if MACH_SUN5I
default 0x4fe00000 if MACH_SUN6I
default 0x4fe00000 if MACH_SUN7I
default 0x4fe00000 if MACH_SUN8I
default 0x2fe00000 if MACH_SUN9I
default 0x4fe00000 if MACH_SUN50I
endif
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