mirror of
https://github.com/AsahiLinux/u-boot
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7ee16de58b
The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the
serial line available via standardised pins on the edge connector and
available on a RS232 connector).
To support boards (such as the RK3399-Q7) that require UART0 as a
debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate
iomux setup to the rk3399 SPL code.
As we are already touching this code, we also move the board-specific
UART setup (i.e. iomux setup) into board_debug_uart_init(). This will
be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT
is set.
As the RK3399 needs to use its board_debug_uart_init() function, we
have Kconfig enable it by default for RK3399 builds.
With everything set up to define CONFIG_BAUDRATE via defconfig and
with to have the SPL debug UART either on UART0 or UART2, the configs
for the RK3399 EVB are then update (the change for the RK3399-Q7 is
left for later to not cause issues on applying the change).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
527 lines
13 KiB
C
527 lines
13 KiB
C
/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __SOC_ROCKCHIP_RK3399_GRF_H__
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#define __SOC_ROCKCHIP_RK3399_GRF_H__
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struct rk3399_grf_regs {
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u32 reserved[0x800];
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u32 usb3_perf_con0;
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u32 usb3_perf_con1;
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u32 usb3_perf_con2;
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u32 usb3_perf_rd_max_latency_num;
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u32 usb3_perf_rd_latency_samp_num;
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u32 usb3_perf_rd_latency_acc_num;
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u32 usb3_perf_rd_axi_total_byte;
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u32 usb3_perf_wr_axi_total_byte;
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u32 usb3_perf_working_cnt;
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u32 reserved1[0x103];
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u32 usb3otg0_con0;
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u32 usb3otg0_con1;
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u32 reserved2[2];
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u32 usb3otg1_con0;
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u32 usb3otg1_con1;
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u32 reserved3[2];
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u32 usb3otg0_status_lat0;
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u32 usb3otg0_status_lat1;
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u32 usb3otg0_status_cb;
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u32 reserved4;
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u32 usb3otg1_status_lat0;
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u32 usb3otg1_status_lat1;
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u32 usb3ogt1_status_cb;
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u32 reserved5[0x6e5];
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u32 pcie_perf_con0;
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u32 pcie_perf_con1;
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u32 pcie_perf_con2;
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u32 pcie_perf_rd_max_latency_num;
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u32 pcie_perf_rd_latency_samp_num;
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u32 pcie_perf_rd_laterncy_acc_num;
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u32 pcie_perf_rd_axi_total_byte;
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u32 pcie_perf_wr_axi_total_byte;
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u32 pcie_perf_working_cnt;
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u32 reserved6[0x37];
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u32 usb20_host0_con0;
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u32 usb20_host0_con1;
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u32 reserved7[2];
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u32 usb20_host1_con0;
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u32 usb20_host1_con1;
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u32 reserved8[2];
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u32 hsic_con0;
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u32 hsic_con1;
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u32 reserved9[6];
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u32 grf_usbhost0_status;
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u32 grf_usbhost1_Status;
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u32 grf_hsic_status;
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u32 reserved10[0xc9];
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u32 hsicphy_con0;
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u32 reserved11[3];
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u32 usbphy0_ctrl[26];
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u32 reserved12[6];
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u32 usbphy1[26];
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u32 reserved13[0x72f];
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u32 soc_con9;
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u32 reserved14[0x0a];
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u32 soc_con20;
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u32 soc_con21;
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u32 soc_con22;
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u32 soc_con23;
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u32 soc_con24;
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u32 soc_con25;
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u32 soc_con26;
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u32 reserved15[0xf65];
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u32 cpu_con[4];
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u32 reserved16[0x1c];
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u32 cpu_status[6];
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u32 reserved17[0x1a];
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u32 a53_perf_con[4];
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u32 a53_perf_rd_mon_st;
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u32 a53_perf_rd_mon_end;
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u32 a53_perf_wr_mon_st;
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u32 a53_perf_wr_mon_end;
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u32 a53_perf_rd_max_latency_num;
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u32 a53_perf_rd_latency_samp_num;
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u32 a53_perf_rd_laterncy_acc_num;
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u32 a53_perf_rd_axi_total_byte;
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u32 a53_perf_wr_axi_total_byte;
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u32 a53_perf_working_cnt;
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u32 a53_perf_int_status;
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u32 reserved18[0x31];
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u32 a72_perf_con[4];
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u32 a72_perf_rd_mon_st;
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u32 a72_perf_rd_mon_end;
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u32 a72_perf_wr_mon_st;
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u32 a72_perf_wr_mon_end;
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u32 a72_perf_rd_max_latency_num;
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u32 a72_perf_rd_latency_samp_num;
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u32 a72_perf_rd_laterncy_acc_num;
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u32 a72_perf_rd_axi_total_byte;
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u32 a72_perf_wr_axi_total_byte;
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u32 a72_perf_working_cnt;
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u32 a72_perf_int_status;
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u32 reserved19[0x7f6];
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u32 soc_con5;
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u32 soc_con6;
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u32 reserved20[0x779];
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u32 gpio2a_iomux;
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union {
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u32 iomux_spi2;
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u32 gpio2b_iomux;
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};
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union {
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u32 gpio2c_iomux;
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u32 iomux_spi5;
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};
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u32 gpio2d_iomux;
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union {
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u32 gpio3a_iomux;
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u32 iomux_spi0;
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};
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u32 gpio3b_iomux;
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u32 gpio3c_iomux;
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union {
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u32 iomux_i2s0;
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u32 gpio3d_iomux;
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};
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union {
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u32 iomux_i2sclk;
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u32 gpio4a_iomux;
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};
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union {
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u32 iomux_sdmmc;
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u32 iomux_uart2a;
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u32 gpio4b_iomux;
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};
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union {
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u32 iomux_pwm_0;
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u32 iomux_pwm_1;
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u32 iomux_uart2b;
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u32 iomux_uart2c;
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u32 iomux_edp_hotplug;
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u32 gpio4c_iomux;
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};
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u32 gpio4d_iomux;
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u32 reserved21[4];
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u32 gpio2_p[4];
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u32 gpio3_p[4];
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u32 gpio4_p[4];
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u32 reserved22[4];
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u32 gpio2_sr[3][4];
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u32 reserved23[4];
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u32 gpio2_smt[3][4];
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u32 reserved24[(0xe130 - 0xe0ec)/4 - 1];
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u32 gpio4b_e01;
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u32 gpio4b_e2;
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u32 reserved24a[(0xe200 - 0xe134)/4 - 1];
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u32 soc_con0;
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u32 soc_con1;
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u32 soc_con2;
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u32 soc_con3;
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u32 soc_con4;
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u32 soc_con5_pcie;
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u32 reserved25;
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u32 soc_con7;
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u32 soc_con8;
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u32 soc_con9_pcie;
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u32 reserved26[0x1e];
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u32 soc_status[6];
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u32 reserved27[0x32];
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u32 ddrc0_con0;
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u32 ddrc0_con1;
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u32 ddrc1_con0;
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u32 ddrc1_con1;
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u32 reserved28[0xac];
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u32 io_vsel;
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u32 saradc_testbit;
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u32 tsadc_testbit_l;
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u32 tsadc_testbit_h;
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u32 reserved29[0x6c];
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u32 chip_id_addr;
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u32 reserved30[0x1f];
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u32 fast_boot_addr;
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u32 reserved31[0x1df];
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u32 emmccore_con[12];
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u32 reserved32[4];
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u32 emmccore_status[4];
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u32 reserved33[0x1cc];
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u32 emmcphy_con[7];
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u32 reserved34;
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u32 emmcphy_status;
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};
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check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0);
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struct rk3399_pmugrf_regs {
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union {
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u32 iomux_pwm_3a;
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u32 gpio0a_iomux;
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};
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u32 gpio0b_iomux;
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u32 reserved0[2];
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union {
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u32 spi1_rxd;
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u32 tsadc_int;
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u32 gpio1a_iomux;
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};
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union {
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u32 spi1_csclktx;
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u32 iomux_pwm_3b;
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u32 iomux_i2c0_sda;
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u32 gpio1b_iomux;
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};
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union {
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u32 iomux_pwm_2;
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u32 iomux_i2c0_scl;
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u32 gpio1c_iomux;
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};
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u32 gpio1d_iomux;
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u32 reserved1[8];
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u32 gpio0_p[2];
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u32 reserved2[2];
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u32 gpio1_p[4];
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u32 reserved3[8];
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u32 gpio0a_e;
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u32 reserved4;
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u32 gpio0b_e;
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u32 reserved5[5];
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u32 gpio1a_e;
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u32 reserved6;
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u32 gpio1b_e;
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u32 reserved7;
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u32 gpio1c_e;
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u32 reserved8;
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u32 gpio1d_e;
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u32 reserved9[0x11];
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u32 gpio0l_sr;
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u32 reserved10;
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u32 gpio1l_sr;
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u32 gpio1h_sr;
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u32 reserved11[4];
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u32 gpio0a_smt;
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u32 gpio0b_smt;
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u32 reserved12[2];
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u32 gpio1a_smt;
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u32 gpio1b_smt;
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u32 gpio1c_smt;
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u32 gpio1d_smt;
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u32 reserved13[8];
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u32 gpio0l_he;
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u32 reserved14;
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u32 gpio1l_he;
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u32 gpio1h_he;
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u32 reserved15[4];
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u32 soc_con0;
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u32 reserved16[9];
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u32 soc_con10;
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u32 soc_con11;
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u32 reserved17[0x24];
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u32 pmupvtm_con0;
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u32 pmupvtm_con1;
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u32 pmupvtm_status0;
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u32 pmupvtm_status1;
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u32 grf_osc_e;
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u32 reserved18[0x2b];
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u32 os_reg0;
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u32 os_reg1;
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u32 os_reg2;
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u32 os_reg3;
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};
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check_member(rk3399_pmugrf_regs, os_reg3, 0x30c);
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struct rk3399_pmusgrf_regs {
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u32 ddr_rgn_con[35];
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u32 reserved[0x1fe5];
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u32 soc_con8;
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u32 soc_con9;
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u32 soc_con10;
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u32 soc_con11;
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u32 soc_con12;
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u32 soc_con13;
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u32 soc_con14;
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u32 soc_con15;
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u32 reserved1[3];
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u32 soc_con19;
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u32 soc_con20;
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u32 soc_con21;
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u32 soc_con22;
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u32 reserved2[0x29];
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u32 perilp_con[9];
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u32 reserved4[7];
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u32 perilp_status;
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u32 reserved5[0xfaf];
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u32 soc_con0;
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u32 soc_con1;
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u32 reserved6[0x3e];
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u32 pmu_con[9];
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u32 reserved7[0x17];
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u32 fast_boot_addr;
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u32 reserved8[0x1f];
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u32 efuse_prg_mask;
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u32 efuse_read_mask;
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u32 reserved9[0x0e];
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u32 pmu_slv_con0;
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u32 pmu_slv_con1;
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u32 reserved10[0x771];
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u32 soc_con3;
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u32 soc_con4;
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u32 soc_con5;
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u32 soc_con6;
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u32 soc_con7;
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u32 reserved11[8];
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u32 soc_con16;
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u32 soc_con17;
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u32 soc_con18;
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u32 reserved12[0xdd];
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u32 slv_secure_con0;
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u32 slv_secure_con1;
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u32 reserved13;
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u32 slv_secure_con2;
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u32 slv_secure_con3;
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u32 slv_secure_con4;
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};
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check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4);
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enum {
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/* GRF_GPIO2B_IOMUX */
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GRF_GPIO2B1_SEL_SHIFT = 0,
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GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT,
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GRF_SPI2TPM_RXD = 1,
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GRF_GPIO2B2_SEL_SHIFT = 2,
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GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT,
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GRF_SPI2TPM_TXD = 1,
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GRF_GPIO2B3_SEL_SHIFT = 6,
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GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT,
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GRF_SPI2TPM_CLK = 1,
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GRF_GPIO2B4_SEL_SHIFT = 8,
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GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT,
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GRF_SPI2TPM_CSN0 = 1,
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/* GRF_GPIO2C_IOMUX */
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GRF_GPIO2C0_SEL_SHIFT = 0,
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GRF_GPIO2C0_SEL_MASK = 3 << GRF_GPIO2C0_SEL_SHIFT,
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GRF_UART0BT_SIN = 1,
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GRF_GPIO2C1_SEL_SHIFT = 2,
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GRF_GPIO2C1_SEL_MASK = 3 << GRF_GPIO2C1_SEL_SHIFT,
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GRF_UART0BT_SOUT = 1,
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/* GRF_GPIO3A_IOMUX */
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GRF_GPIO3A0_SEL_SHIFT = 0,
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GRF_GPIO3A0_SEL_MASK = 3 << GRF_GPIO3A0_SEL_SHIFT,
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GRF_MAC_TXD2 = 1,
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GRF_GPIO3A1_SEL_SHIFT = 2,
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GRF_GPIO3A1_SEL_MASK = 3 << GRF_GPIO3A1_SEL_SHIFT,
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GRF_MAC_TXD3 = 1,
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GRF_GPIO3A2_SEL_SHIFT = 4,
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GRF_GPIO3A2_SEL_MASK = 3 << GRF_GPIO3A2_SEL_SHIFT,
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GRF_MAC_RXD2 = 1,
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GRF_GPIO3A3_SEL_SHIFT = 6,
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GRF_GPIO3A3_SEL_MASK = 3 << GRF_GPIO3A3_SEL_SHIFT,
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GRF_MAC_RXD3 = 1,
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GRF_GPIO3A4_SEL_SHIFT = 8,
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GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT,
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GRF_MAC_TXD0 = 1,
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GRF_SPI0NORCODEC_RXD = 2,
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GRF_GPIO3A5_SEL_SHIFT = 10,
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GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT,
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GRF_MAC_TXD1 = 1,
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GRF_SPI0NORCODEC_TXD = 2,
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GRF_GPIO3A6_SEL_SHIFT = 12,
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GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT,
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GRF_MAC_RXD0 = 1,
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GRF_SPI0NORCODEC_CLK = 2,
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GRF_GPIO3A7_SEL_SHIFT = 14,
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GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT,
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GRF_MAC_RXD1 = 1,
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GRF_SPI0NORCODEC_CSN0 = 2,
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/* GRF_GPIO3B_IOMUX */
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GRF_GPIO3B0_SEL_SHIFT = 0,
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GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT,
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GRF_MAC_MDC = 1,
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GRF_SPI0NORCODEC_CSN1 = 2,
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GRF_GPIO3B1_SEL_SHIFT = 2,
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GRF_GPIO3B1_SEL_MASK = 3 << GRF_GPIO3B1_SEL_SHIFT,
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GRF_MAC_RXDV = 1,
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GRF_GPIO3B3_SEL_SHIFT = 6,
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GRF_GPIO3B3_SEL_MASK = 3 << GRF_GPIO3B3_SEL_SHIFT,
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GRF_MAC_CLK = 1,
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GRF_GPIO3B4_SEL_SHIFT = 8,
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GRF_GPIO3B4_SEL_MASK = 3 << GRF_GPIO3B4_SEL_SHIFT,
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GRF_MAC_TXEN = 1,
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GRF_GPIO3B5_SEL_SHIFT = 10,
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GRF_GPIO3B5_SEL_MASK = 3 << GRF_GPIO3B5_SEL_SHIFT,
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GRF_MAC_MDIO = 1,
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GRF_GPIO3B6_SEL_SHIFT = 12,
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GRF_GPIO3B6_SEL_MASK = 3 << GRF_GPIO3B6_SEL_SHIFT,
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GRF_MAC_RXCLK = 1,
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/* GRF_GPIO3C_IOMUX */
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GRF_GPIO3C1_SEL_SHIFT = 2,
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GRF_GPIO3C1_SEL_MASK = 3 << GRF_GPIO3C1_SEL_SHIFT,
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GRF_MAC_TXCLK = 1,
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/* GRF_GPIO4B_IOMUX */
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GRF_GPIO4B0_SEL_SHIFT = 0,
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GRF_GPIO4B0_SEL_MASK = 3 << GRF_GPIO4B0_SEL_SHIFT,
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GRF_SDMMC_DATA0 = 1,
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GRF_UART2DBGA_SIN = 2,
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GRF_GPIO4B1_SEL_SHIFT = 2,
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GRF_GPIO4B1_SEL_MASK = 3 << GRF_GPIO4B1_SEL_SHIFT,
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GRF_SDMMC_DATA1 = 1,
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GRF_UART2DBGA_SOUT = 2,
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GRF_GPIO4B2_SEL_SHIFT = 4,
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GRF_GPIO4B2_SEL_MASK = 3 << GRF_GPIO4B2_SEL_SHIFT,
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GRF_SDMMC_DATA2 = 1,
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GRF_GPIO4B3_SEL_SHIFT = 6,
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GRF_GPIO4B3_SEL_MASK = 3 << GRF_GPIO4B3_SEL_SHIFT,
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GRF_SDMMC_DATA3 = 1,
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GRF_GPIO4B4_SEL_SHIFT = 8,
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GRF_GPIO4B4_SEL_MASK = 3 << GRF_GPIO4B4_SEL_SHIFT,
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GRF_SDMMC_CLKOUT = 1,
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GRF_GPIO4B5_SEL_SHIFT = 10,
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GRF_GPIO4B5_SEL_MASK = 3 << GRF_GPIO4B5_SEL_SHIFT,
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GRF_SDMMC_CMD = 1,
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/* GRF_GPIO4C_IOMUX */
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GRF_GPIO4C0_SEL_SHIFT = 0,
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GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT,
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GRF_UART2DGBB_SIN = 2,
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GRF_GPIO4C1_SEL_SHIFT = 2,
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GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT,
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GRF_UART2DGBB_SOUT = 2,
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GRF_GPIO4C2_SEL_SHIFT = 4,
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GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT,
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GRF_PWM_0 = 1,
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GRF_GPIO4C3_SEL_SHIFT = 6,
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GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT,
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GRF_UART2DGBC_SIN = 1,
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GRF_GPIO4C4_SEL_SHIFT = 8,
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GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT,
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GRF_UART2DBGC_SOUT = 1,
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GRF_GPIO4C6_SEL_SHIFT = 12,
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GRF_GPIO4C6_SEL_MASK = 3 << GRF_GPIO4C6_SEL_SHIFT,
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GRF_PWM_1 = 1,
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/* GRF_SOC_CON7 */
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GRF_UART_DBG_SEL_SHIFT = 10,
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GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT,
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GRF_UART_DBG_SEL_C = 2,
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/* PMUGRF_GPIO0A_IOMUX */
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PMUGRF_GPIO0A6_SEL_SHIFT = 12,
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PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,
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PMUGRF_PWM_3A = 1,
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/* PMUGRF_GPIO1A_IOMUX */
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PMUGRF_GPIO1A7_SEL_SHIFT = 14,
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PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT,
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PMUGRF_SPI1EC_RXD = 2,
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/* PMUGRF_GPIO1B_IOMUX */
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PMUGRF_GPIO1B0_SEL_SHIFT = 0,
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PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT,
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PMUGRF_SPI1EC_TXD = 2,
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PMUGRF_GPIO1B1_SEL_SHIFT = 2,
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PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT,
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PMUGRF_SPI1EC_CLK = 2,
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PMUGRF_GPIO1B2_SEL_SHIFT = 4,
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PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT,
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PMUGRF_SPI1EC_CSN0 = 2,
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PMUGRF_GPIO1B6_SEL_SHIFT = 12,
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PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT,
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PMUGRF_PWM_3B = 1,
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PMUGRF_GPIO1B7_SEL_SHIFT = 14,
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PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT,
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PMUGRF_I2C0PMU_SDA = 2,
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|
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/* PMUGRF_GPIO1C_IOMUX */
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PMUGRF_GPIO1C0_SEL_SHIFT = 0,
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PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT,
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PMUGRF_I2C0PMU_SCL = 2,
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PMUGRF_GPIO1C3_SEL_SHIFT = 6,
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PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT,
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PMUGRF_PWM_2 = 1,
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|
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};
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/* GRF_SOC_CON5 */
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enum {
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RK3399_GMAC_PHY_INTF_SEL_SHIFT = 9,
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RK3399_GMAC_PHY_INTF_SEL_MASK = (7 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
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RK3399_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
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RK3399_GMAC_PHY_INTF_SEL_RMII = (4 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
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RK3399_GMAC_CLK_SEL_SHIFT = 4,
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RK3399_GMAC_CLK_SEL_MASK = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
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RK3399_GMAC_CLK_SEL_125M = (0 << RK3399_GMAC_CLK_SEL_SHIFT),
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RK3399_GMAC_CLK_SEL_25M = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
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RK3399_GMAC_CLK_SEL_2_5M = (2 << RK3399_GMAC_CLK_SEL_SHIFT),
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};
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|
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/* GRF_SOC_CON6 */
|
|
enum {
|
|
RK3399_RXCLK_DLY_ENA_GMAC_SHIFT = 15,
|
|
RK3399_RXCLK_DLY_ENA_GMAC_MASK =
|
|
(1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
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|
RK3399_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
|
|
RK3399_RXCLK_DLY_ENA_GMAC_ENABLE =
|
|
(1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
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|
|
|
RK3399_TXCLK_DLY_ENA_GMAC_SHIFT = 7,
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|
RK3399_TXCLK_DLY_ENA_GMAC_MASK =
|
|
(1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
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|
RK3399_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
|
|
RK3399_TXCLK_DLY_ENA_GMAC_ENABLE =
|
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(1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
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|
|
|
RK3399_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
|
|
RK3399_CLK_RX_DL_CFG_GMAC_MASK =
|
|
(0x7f << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT),
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|
|
|
RK3399_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
|
|
RK3399_CLK_TX_DL_CFG_GMAC_MASK =
|
|
(0x7f << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT),
|
|
};
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#endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */
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