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u-boot/arch/mips/cpu/mips32
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Daniel Schwierzeck ab2a98b117 MIPS: make cache operation mode configurable 
Currently the cache operation mode is hard-coded to
CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs
which operate at a different mode.

This patch makes the cache operation mode configurable via board config.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Acked-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-07-31 23:26:41 +09:00
..
au1x00 MIPS: Au1x00: Move all Au1x00 specific code to separate subdirectory 2011-04-02 22:07:12 +09:00
incaip MIPS: IncaIP: Move all IncaIP specific code to separate subdirectory 2011-04-02 22:07:12 +09:00
cache.S MIPS: Coding style cleanups on common assembly files 2011-05-07 00:18:13 +09:00
config.mk MIPS: Optimize the setup of CPU optimization flags 2011-04-02 22:07:12 +09:00
cpu.c MIPS: Move content of arch/mips/cpu to arch/mips/cpu/mips32 2011-04-02 22:07:12 +09:00
interrupts.c MIPS: Move content of arch/mips/cpu to arch/mips/cpu/mips32 2011-04-02 22:07:12 +09:00
Makefile MIPS: Move timer code to arch/mips/cpu/$(CPU)/ 2011-05-10 00:12:31 +09:00
start.S MIPS: make cache operation mode configurable 2011-07-31 23:26:41 +09:00
time.c Timer: Remove reset_timer() for non-Nios2 arches 2011-07-26 14:53:30 +02:00