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Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
466 lines
11 KiB
C
466 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* max98095.c -- MAX98095 ALSA SoC Audio driver
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*
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* Copyright 2011 Maxim Integrated Products
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*
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* Modified for U-Boot by R. Chandrasekar (rcsekar@samsung.com)
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*/
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#include <common.h>
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#include <audio_codec.h>
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#include <dm.h>
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#include <div64.h>
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#include <fdtdec.h>
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#include <i2c.h>
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#include <log.h>
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#include <sound.h>
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#include <asm/gpio.h>
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#include "i2s.h"
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#include "max98095.h"
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/* Index 0 is reserved. */
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int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
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88200, 96000};
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/*
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* codec mclk clock divider coefficients based on sampling rate
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*
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* @param rate sampling rate
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* @param value address of indexvalue to be stored
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*
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* Return: 0 for success or negative error code.
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*/
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static int rate_value(int rate, u8 *value)
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{
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int i;
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for (i = 1; i < ARRAY_SIZE(rate_table); i++) {
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if (rate_table[i] >= rate) {
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*value = i;
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return 0;
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}
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}
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*value = 1;
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return -EINVAL;
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}
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/*
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* Sets hw params for max98095
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*
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* @param priv max98095 information pointer
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* @param rate Sampling rate
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* @param bits_per_sample Bits per sample
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*
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* Return: 0 for success or negative error code.
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*/
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static int max98095_hw_params(struct maxim_priv *priv,
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enum en_max_audio_interface aif_id,
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unsigned int rate, unsigned int bits_per_sample)
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{
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u8 regval;
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int error;
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unsigned short M98095_DAI_CLKMODE;
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unsigned short M98095_DAI_FORMAT;
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unsigned short M98095_DAI_FILTERS;
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if (aif_id == AIF1) {
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M98095_DAI_CLKMODE = M98095_027_DAI1_CLKMODE;
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M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
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M98095_DAI_FILTERS = M98095_02E_DAI1_FILTERS;
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} else {
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M98095_DAI_CLKMODE = M98095_031_DAI2_CLKMODE;
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M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
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M98095_DAI_FILTERS = M98095_038_DAI2_FILTERS;
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}
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switch (bits_per_sample) {
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case 16:
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error = maxim_bic_or(priv, M98095_DAI_FORMAT, M98095_DAI_WS, 0);
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break;
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case 24:
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error = maxim_bic_or(priv, M98095_DAI_FORMAT, M98095_DAI_WS,
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M98095_DAI_WS);
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break;
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default:
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debug("%s: Illegal bits per sample %d.\n",
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__func__, bits_per_sample);
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return -EINVAL;
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}
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if (rate_value(rate, ®val)) {
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debug("%s: Failed to set sample rate to %d.\n",
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__func__, rate);
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return -EINVAL;
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}
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priv->rate = rate;
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error |= maxim_bic_or(priv, M98095_DAI_CLKMODE, M98095_CLKMODE_MASK,
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regval);
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/* Update sample rate mode */
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if (rate < 50000)
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error |= maxim_bic_or(priv, M98095_DAI_FILTERS,
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M98095_DAI_DHF, 0);
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else
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error |= maxim_bic_or(priv, M98095_DAI_FILTERS,
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M98095_DAI_DHF, M98095_DAI_DHF);
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if (error < 0) {
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debug("%s: Error setting hardware params.\n", __func__);
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return -EIO;
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}
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return 0;
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}
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/*
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* Configures Audio interface system clock for the given frequency
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*
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* @param priv max98095 information
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* @param freq Sampling frequency in Hz
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*
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* Return: 0 for success or negative error code.
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*/
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static int max98095_set_sysclk(struct maxim_priv *priv, unsigned int freq)
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{
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int error = 0;
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/* Requested clock frequency is already setup */
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if (freq == priv->sysclk)
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return 0;
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/* Setup clocks for slave mode, and using the PLL
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* PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
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* 0x02 (when master clk is 20MHz to 40MHz)..
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* 0x03 (when master clk is 40MHz to 60MHz)..
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*/
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if ((freq >= 10000000) && (freq < 20000000)) {
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error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x10);
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} else if ((freq >= 20000000) && (freq < 40000000)) {
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error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x20);
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} else if ((freq >= 40000000) && (freq < 60000000)) {
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error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x30);
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} else {
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debug("%s: Invalid master clock frequency\n", __func__);
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return -EINVAL;
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}
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debug("%s: Clock at %uHz\n", __func__, freq);
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if (error < 0)
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return -EIO;
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priv->sysclk = freq;
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return 0;
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}
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/*
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* Sets Max98095 I2S format
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*
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* @param priv max98095 information
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* @param fmt i2S format - supports a subset of the options defined
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* in i2s.h.
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*
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* Return: 0 for success or negative error code.
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*/
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static int max98095_set_fmt(struct maxim_priv *priv, int fmt,
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enum en_max_audio_interface aif_id)
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{
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u8 regval = 0;
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int error = 0;
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unsigned short M98095_DAI_CLKCFG_HI;
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unsigned short M98095_DAI_CLKCFG_LO;
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unsigned short M98095_DAI_FORMAT;
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unsigned short M98095_DAI_CLOCK;
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if (fmt == priv->fmt)
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return 0;
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priv->fmt = fmt;
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if (aif_id == AIF1) {
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M98095_DAI_CLKCFG_HI = M98095_028_DAI1_CLKCFG_HI;
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M98095_DAI_CLKCFG_LO = M98095_029_DAI1_CLKCFG_LO;
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M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
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M98095_DAI_CLOCK = M98095_02B_DAI1_CLOCK;
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} else {
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M98095_DAI_CLKCFG_HI = M98095_032_DAI2_CLKCFG_HI;
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M98095_DAI_CLKCFG_LO = M98095_033_DAI2_CLKCFG_LO;
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M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
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M98095_DAI_CLOCK = M98095_035_DAI2_CLOCK;
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}
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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/* Slave mode PLL */
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error |= maxim_i2c_write(priv, M98095_DAI_CLKCFG_HI, 0x80);
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error |= maxim_i2c_write(priv, M98095_DAI_CLKCFG_LO, 0x00);
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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/* Set to master mode */
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regval |= M98095_DAI_MAS;
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break;
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case SND_SOC_DAIFMT_CBS_CFM:
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case SND_SOC_DAIFMT_CBM_CFS:
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default:
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debug("%s: Clock mode unsupported\n", __func__);
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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regval |= M98095_DAI_DLY;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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break;
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default:
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debug("%s: Unrecognized format.\n", __func__);
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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break;
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case SND_SOC_DAIFMT_NB_IF:
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regval |= M98095_DAI_WCI;
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break;
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case SND_SOC_DAIFMT_IB_NF:
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regval |= M98095_DAI_BCI;
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break;
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case SND_SOC_DAIFMT_IB_IF:
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regval |= M98095_DAI_BCI | M98095_DAI_WCI;
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break;
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default:
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debug("%s: Unrecognized inversion settings.\n", __func__);
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return -EINVAL;
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}
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error |= maxim_bic_or(priv, M98095_DAI_FORMAT,
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M98095_DAI_MAS | M98095_DAI_DLY |
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M98095_DAI_BCI | M98095_DAI_WCI, regval);
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error |= maxim_i2c_write(priv, M98095_DAI_CLOCK, M98095_DAI_BSEL64);
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if (error < 0) {
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debug("%s: Error setting i2s format.\n", __func__);
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return -EIO;
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}
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return 0;
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}
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/*
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* resets the audio codec
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*
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* @param priv Private data for driver
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* Return: 0 for success or negative error code.
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*/
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static int max98095_reset(struct maxim_priv *priv)
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{
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int i, ret;
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/*
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* Gracefully reset the DSP core and the codec hardware in a proper
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* sequence.
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*/
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ret = maxim_i2c_write(priv, M98095_00F_HOST_CFG, 0);
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if (ret != 0) {
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debug("%s: Failed to reset DSP: %d\n", __func__, ret);
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return ret;
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}
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ret = maxim_i2c_write(priv, M98095_097_PWR_SYS, 0);
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if (ret != 0) {
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debug("%s: Failed to reset codec: %d\n", __func__, ret);
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return ret;
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}
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/*
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* Reset to hardware default for registers, as there is not a soft
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* reset hardware control register.
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*/
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for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
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ret = maxim_i2c_write(priv, i, 0);
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if (ret < 0) {
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debug("%s: Failed to reset: %d\n", __func__, ret);
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return ret;
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}
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}
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return 0;
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}
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/*
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* Intialise max98095 codec device
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*
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* @param priv max98095 information
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* Return: 0 for success or negative error code.
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*/
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static int max98095_device_init(struct maxim_priv *priv)
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{
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unsigned char id;
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int ret;
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/* reset the codec, the DSP core, and disable all interrupts */
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ret = max98095_reset(priv);
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if (ret != 0) {
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debug("Reset\n");
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return ret;
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}
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/* initialize private data */
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priv->sysclk = -1U;
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priv->rate = -1U;
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priv->fmt = -1U;
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ret = maxim_i2c_read(priv, M98095_0FF_REV_ID, &id);
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if (ret < 0) {
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debug("%s: Failure reading hardware revision: %d\n",
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__func__, id);
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return ret;
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}
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debug("%s: Hardware revision: %c\n", __func__, (id - 0x40) + 'A');
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return 0;
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}
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static int max98095_setup_interface(struct maxim_priv *priv,
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enum en_max_audio_interface aif_id)
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{
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int error;
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error = maxim_i2c_write(priv, M98095_097_PWR_SYS, M98095_PWRSV);
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/*
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* initialize registers to hardware default configuring audio
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* interface2 to DAC
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*/
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if (aif_id == AIF1)
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error |= maxim_i2c_write(priv, M98095_048_MIX_DAC_LR,
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M98095_DAI1L_TO_DACL |
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M98095_DAI1R_TO_DACR);
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else
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error |= maxim_i2c_write(priv, M98095_048_MIX_DAC_LR,
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M98095_DAI2M_TO_DACL |
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M98095_DAI2M_TO_DACR);
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error |= maxim_i2c_write(priv, M98095_092_PWR_EN_OUT,
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M98095_SPK_SPREADSPECTRUM);
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error |= maxim_i2c_write(priv, M98095_04E_CFG_HP, M98095_HPNORMAL);
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if (aif_id == AIF1)
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error |= maxim_i2c_write(priv, M98095_02C_DAI1_IOCFG,
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M98095_S1NORMAL | M98095_SDATA);
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else
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error |= maxim_i2c_write(priv, M98095_036_DAI2_IOCFG,
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M98095_S2NORMAL | M98095_SDATA);
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/* take the codec out of the shut down */
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error |= maxim_bic_or(priv, M98095_097_PWR_SYS, M98095_SHDNRUN,
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M98095_SHDNRUN);
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/*
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* route DACL and DACR output to HO and Speakers
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* Ordering: DACL, DACR, DACL, DACR
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*/
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error |= maxim_i2c_write(priv, M98095_050_MIX_SPK_LEFT, 0x01);
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error |= maxim_i2c_write(priv, M98095_051_MIX_SPK_RIGHT, 0x01);
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error |= maxim_i2c_write(priv, M98095_04C_MIX_HP_LEFT, 0x01);
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error |= maxim_i2c_write(priv, M98095_04D_MIX_HP_RIGHT, 0x01);
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/* power Enable */
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error |= maxim_i2c_write(priv, M98095_091_PWR_EN_OUT, 0xF3);
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/* set Volume */
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error |= maxim_i2c_write(priv, M98095_064_LVL_HP_L, 15);
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error |= maxim_i2c_write(priv, M98095_065_LVL_HP_R, 15);
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error |= maxim_i2c_write(priv, M98095_067_LVL_SPK_L, 16);
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error |= maxim_i2c_write(priv, M98095_068_LVL_SPK_R, 16);
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/* Enable DAIs */
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error |= maxim_i2c_write(priv, M98095_093_BIAS_CTRL, 0x30);
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if (aif_id == AIF1)
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error |= maxim_i2c_write(priv, M98095_096_PWR_DAC_CK, 0x01);
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else
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error |= maxim_i2c_write(priv, M98095_096_PWR_DAC_CK, 0x07);
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if (error < 0)
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return -EIO;
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return 0;
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}
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static int max98095_do_init(struct maxim_priv *priv,
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enum en_max_audio_interface aif_id,
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int sampling_rate, int mclk_freq,
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int bits_per_sample)
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{
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int ret = 0;
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ret = max98095_setup_interface(priv, aif_id);
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if (ret < 0) {
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debug("%s: max98095 setup interface failed\n", __func__);
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return ret;
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}
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ret = max98095_set_sysclk(priv, mclk_freq);
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if (ret < 0) {
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debug("%s: max98095 codec set sys clock failed\n", __func__);
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return ret;
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}
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ret = max98095_hw_params(priv, aif_id, sampling_rate,
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bits_per_sample);
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if (ret == 0) {
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ret = max98095_set_fmt(priv, SND_SOC_DAIFMT_I2S |
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SND_SOC_DAIFMT_NB_NF |
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SND_SOC_DAIFMT_CBS_CFS,
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aif_id);
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}
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return ret;
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}
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static int max98095_set_params(struct udevice *dev, int interface, int rate,
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int mclk_freq, int bits_per_sample,
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uint channels)
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{
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struct maxim_priv *priv = dev_get_priv(dev);
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return max98095_do_init(priv, interface, rate, mclk_freq,
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bits_per_sample);
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}
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static int max98095_probe(struct udevice *dev)
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{
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struct maxim_priv *priv = dev_get_priv(dev);
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int ret;
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priv->dev = dev;
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ret = max98095_device_init(priv);
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if (ret < 0) {
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debug("%s: max98095 codec chip init failed\n", __func__);
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return ret;
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}
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return 0;
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}
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static const struct audio_codec_ops max98095_ops = {
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.set_params = max98095_set_params,
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};
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static const struct udevice_id max98095_ids[] = {
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{ .compatible = "maxim,max98095" },
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{ }
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};
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U_BOOT_DRIVER(max98095) = {
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.name = "max98095",
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.id = UCLASS_AUDIO_CODEC,
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.of_match = max98095_ids,
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.probe = max98095_probe,
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.ops = &max98095_ops,
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.priv_auto = sizeof(struct maxim_priv),
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};
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