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b9a91b98e8
Since the D1 CCU binding is defined, we can add support for its gates/resets, following the pattern of the existing drivers. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
235 lines
6 KiB
C
235 lines
6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Amarula Solutions.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <reset.h>
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#include <asm/io.h>
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#include <clk/sunxi.h>
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#include <dm/device-internal.h>
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#include <linux/bitops.h>
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#include <linux/log2.h>
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extern U_BOOT_DRIVER(sunxi_reset);
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static const struct ccu_clk_gate *plat_to_gate(struct ccu_plat *plat,
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unsigned long id)
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{
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if (id >= plat->desc->num_gates)
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return NULL;
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return &plat->desc->gates[id];
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}
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static int sunxi_set_gate(struct clk *clk, bool on)
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{
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struct ccu_plat *plat = dev_get_plat(clk->dev);
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const struct ccu_clk_gate *gate = plat_to_gate(plat, clk->id);
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u32 reg;
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if (gate && (gate->flags & CCU_CLK_F_DUMMY_GATE))
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return 0;
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if (!gate || !(gate->flags & CCU_CLK_F_IS_VALID)) {
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printf("%s: (CLK#%ld) unhandled\n", __func__, clk->id);
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return 0;
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}
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debug("%s: (CLK#%ld) off#0x%x, BIT(%d)\n", __func__,
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clk->id, gate->off, ilog2(gate->bit));
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reg = readl(plat->base + gate->off);
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if (on)
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reg |= gate->bit;
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else
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reg &= ~gate->bit;
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writel(reg, plat->base + gate->off);
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return 0;
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}
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static int sunxi_clk_enable(struct clk *clk)
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{
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return sunxi_set_gate(clk, true);
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}
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static int sunxi_clk_disable(struct clk *clk)
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{
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return sunxi_set_gate(clk, false);
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}
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struct clk_ops sunxi_clk_ops = {
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.enable = sunxi_clk_enable,
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.disable = sunxi_clk_disable,
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};
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static int sunxi_clk_bind(struct udevice *dev)
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{
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/* Reuse the platform data for the reset driver. */
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return device_bind(dev, DM_DRIVER_REF(sunxi_reset), "reset",
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dev_get_plat(dev), dev_ofnode(dev), NULL);
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}
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static int sunxi_clk_probe(struct udevice *dev)
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{
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struct clk_bulk clk_bulk;
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struct reset_ctl_bulk rst_bulk;
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int ret;
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ret = clk_get_bulk(dev, &clk_bulk);
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if (!ret)
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clk_enable_bulk(&clk_bulk);
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ret = reset_get_bulk(dev, &rst_bulk);
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if (!ret)
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reset_deassert_bulk(&rst_bulk);
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return 0;
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}
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static int sunxi_clk_of_to_plat(struct udevice *dev)
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{
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struct ccu_plat *plat = dev_get_plat(dev);
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plat->base = dev_read_addr_ptr(dev);
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if (!plat->base)
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return -ENOMEM;
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plat->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
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if (!plat->desc)
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return -EINVAL;
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return 0;
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}
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extern const struct ccu_desc a10_ccu_desc;
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extern const struct ccu_desc a10s_ccu_desc;
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extern const struct ccu_desc a23_ccu_desc;
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extern const struct ccu_desc a31_ccu_desc;
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extern const struct ccu_desc a31_r_ccu_desc;
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extern const struct ccu_desc a64_ccu_desc;
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extern const struct ccu_desc a80_ccu_desc;
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extern const struct ccu_desc a80_mmc_clk_desc;
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extern const struct ccu_desc a83t_ccu_desc;
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extern const struct ccu_desc d1_ccu_desc;
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extern const struct ccu_desc f1c100s_ccu_desc;
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extern const struct ccu_desc h3_ccu_desc;
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extern const struct ccu_desc h6_ccu_desc;
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extern const struct ccu_desc h616_ccu_desc;
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extern const struct ccu_desc h6_r_ccu_desc;
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extern const struct ccu_desc r40_ccu_desc;
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extern const struct ccu_desc v3s_ccu_desc;
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static const struct udevice_id sunxi_clk_ids[] = {
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#ifdef CONFIG_CLK_SUN4I_A10
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{ .compatible = "allwinner,sun4i-a10-ccu",
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.data = (ulong)&a10_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUN5I_A10S
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{ .compatible = "allwinner,sun5i-a10s-ccu",
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.data = (ulong)&a10s_ccu_desc },
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{ .compatible = "allwinner,sun5i-a13-ccu",
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.data = (ulong)&a10s_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUN6I_A31
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{ .compatible = "allwinner,sun6i-a31-ccu",
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.data = (ulong)&a31_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUN4I_A10
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{ .compatible = "allwinner,sun7i-a20-ccu",
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.data = (ulong)&a10_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUN8I_A23
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{ .compatible = "allwinner,sun8i-a23-ccu",
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.data = (ulong)&a23_ccu_desc },
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{ .compatible = "allwinner,sun8i-a33-ccu",
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.data = (ulong)&a23_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUN8I_A83T
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{ .compatible = "allwinner,sun8i-a83t-ccu",
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.data = (ulong)&a83t_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUN6I_A31_R
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{ .compatible = "allwinner,sun8i-a83t-r-ccu",
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.data = (ulong)&a31_r_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUN8I_H3
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{ .compatible = "allwinner,sun8i-h3-ccu",
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.data = (ulong)&h3_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUN6I_A31_R
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{ .compatible = "allwinner,sun8i-h3-r-ccu",
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.data = (ulong)&a31_r_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUN8I_R40
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{ .compatible = "allwinner,sun8i-r40-ccu",
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.data = (ulong)&r40_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUN8I_V3S
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{ .compatible = "allwinner,sun8i-v3-ccu",
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.data = (ulong)&v3s_ccu_desc },
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{ .compatible = "allwinner,sun8i-v3s-ccu",
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.data = (ulong)&v3s_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUN9I_A80
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{ .compatible = "allwinner,sun9i-a80-ccu",
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.data = (ulong)&a80_ccu_desc },
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{ .compatible = "allwinner,sun9i-a80-mmc-config-clk",
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.data = (ulong)&a80_mmc_clk_desc },
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#endif
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#ifdef CONFIG_CLK_SUN50I_A64
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{ .compatible = "allwinner,sun50i-a64-ccu",
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.data = (ulong)&a64_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUN6I_A31_R
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{ .compatible = "allwinner,sun50i-a64-r-ccu",
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.data = (ulong)&a31_r_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUN8I_H3
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{ .compatible = "allwinner,sun50i-h5-ccu",
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.data = (ulong)&h3_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUN20I_D1
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{ .compatible = "allwinner,sun20i-d1-ccu",
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.data = (ulong)&d1_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUN50I_H6
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{ .compatible = "allwinner,sun50i-h6-ccu",
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.data = (ulong)&h6_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUN50I_H6_R
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{ .compatible = "allwinner,sun50i-h6-r-ccu",
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.data = (ulong)&h6_r_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUN50I_H616
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{ .compatible = "allwinner,sun50i-h616-ccu",
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.data = (ulong)&h616_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUN50I_H6_R
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{ .compatible = "allwinner,sun50i-h616-r-ccu",
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.data = (ulong)&h6_r_ccu_desc },
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#endif
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#ifdef CONFIG_CLK_SUNIV_F1C100S
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{ .compatible = "allwinner,suniv-f1c100s-ccu",
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.data = (ulong)&f1c100s_ccu_desc },
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#endif
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{ }
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};
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U_BOOT_DRIVER(sunxi_clk) = {
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.name = "sunxi_clk",
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.id = UCLASS_CLK,
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.of_match = sunxi_clk_ids,
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.bind = sunxi_clk_bind,
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.probe = sunxi_clk_probe,
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.of_to_plat = sunxi_clk_of_to_plat,
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.plat_auto = sizeof(struct ccu_plat),
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.ops = &sunxi_clk_ops,
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};
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