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https://github.com/AsahiLinux/u-boot
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cfc2587462
This patch removes the Sequoia "bootstrap" command and replaces it with the now common command "chip_config". Please note that the patches with the dynamic PCI sync clock configuration have to be applied, before this one should go in. This is because Sequoia has 2 different bootstrap EEPROMs, and the old bootstrap command configured different values depending on the detected PCI async clock (33 vs. 66MHz). With the PCI sync clock patches, this is not necessary anymore. The PCI sync clock will be configured correctly on-the-fly now. Signed-off-by: Stefan Roese <sr@denx.de>
122 lines
3.3 KiB
C
122 lines
3.3 KiB
C
/*
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* (C) Copyright 2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <asm/ppc4xx_config.h>
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struct ppc4xx_config ppc4xx_config_val[] = {
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{
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"333-133-nor", "NOR CPU: 333 PLB: 133 OPB: 66 EBC: 66",
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{
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0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10,
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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}
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},
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{
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"333-166-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 55",
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{
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0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30,
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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}
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},
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{
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"333-166-nand", "NAND CPU: 333 PLB: 166 OPB: 83 EBC: 55",
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{
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0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xd0, 0x30,
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0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
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}
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},
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{
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"400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66",
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{
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0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30,
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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}
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},
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{
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"400-160-nor", "NOR CPU: 400 PLB: 160 OPB: 80 EBC: 53",
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{
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0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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}
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},
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{
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"416-166-nor", "NOR CPU: 416 PLB: 166 OPB: 83 EBC: 55",
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{
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0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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}
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},
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{
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"416-166-nand", "NAND CPU: 416 PLB: 166 OPB: 83 EBC: 55",
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{
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0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xd0, 0x10,
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0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
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}
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},
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{
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"500-166-nor", "NOR CPU: 500 PLB: 166 OPB: 83 EBC: 55",
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{
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0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30,
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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}
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},
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{
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"500-166-nand", "NAND CPU: 500 PLB: 166 OPB: 83 EBC: 55",
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{
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0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xd0, 0x30,
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0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
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}
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},
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{
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"533-133-nor", "NOR CPU: 533 PLB: 133 OPB: 66 EBC: 66",
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{
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0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30,
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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}
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},
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{
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"667-133-nor", "NOR CPU: 667 PLB: 133 OPB: 66 EBC: 66",
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{
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0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30,
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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}
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},
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{
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"667-166-nor", "NOR CPU: 667 PLB: 166 OPB: 83 EBC: 55",
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{
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0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30,
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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}
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},
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{
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"667-166-nand", "NAND CPU: 667 PLB: 166 OPB: 83 EBC: 55",
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{
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0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x30,
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0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
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}
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},
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};
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int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
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