mirror of
https://github.com/AsahiLinux/u-boot
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c9135d5a7a
Previous device tree for OpenPiton emits a warning during compilation. This commit fixes the previous warning adds dts to the OpenPiton RISC-V board and added the device tree to MAINTAINER file. Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Reported-by: Tom Rini <trini@konsulko.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
153 lines
3.6 KiB
Text
153 lines
3.6 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2021 Tianrui Wei <tianrui-wei@outlook.com> */
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/*
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* This dts is for a dual core instance of OpenPiton+Ariane built
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* to run on a Digilent Genesys 2 FPGA at 66.67MHz. These files
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* are automatically generated by the OpenPiton build system and
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* this configuration may not be what you need if your configuration
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* is different from the below.
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "openpiton,riscv64";
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chosen {
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stdout-path = "uart0:115200";
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};
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aliases {
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console = &uart0;
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serial0 = &uart0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <520835>;
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CPU0: cpu@0 {
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clocks = <&clk0>;
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u-boot,dm-spl;
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device_type = "cpu";
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reg = <0>;
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compatible = "openhwgroup,cva6", "riscv";
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv39";
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tlb-split;
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// HLIC - hart local interrupt controller
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CPU0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU1: cpu@1 {
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clocks = <&clk0>;
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device_type = "cpu";
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reg = <1>;
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compatible = "openhwgroup,cva6", "riscv";
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv39";
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tlb-split;
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// HLIC - hart local interrupt controller
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CPU1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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clocks {
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clk0: osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <66667000>;
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};
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};
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memory@80000000 {
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u-boot,dm-spl;
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device_type = "memory";
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reg = < 0x00000000 0x80000000 0x00000000 0x40000000 >;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "openpiton,chipset", "simple-bus";
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ranges;
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uart0: uart@fff0c2c000 {
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compatible = "ns16550", "openpiton,ns16550";
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reg = < 0x000000ff 0xf0c2c000 0x00000000 0x000d4000 >;
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interrupt-parent = <&PLIC0>;
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interrupts = <1>;
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reg-shift = <0>;
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// regs are spaced on 8 bit boundary
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};
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eth: ethernet@fff0d00000 {
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compatible = "xlnx,xps-ethernetlite-1.00.a", "openpiton,ethernet";
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device_type = "network";
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reg = < 0x000000ff 0xf0d00000 0x00000000 0x00100000 >;
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interrupt-parent = <&PLIC0>;
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interrupts = <2>;
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phy-handle = <&phy0>;
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xlnx,duplex = <0x1>;
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xlnx,include-global-buffers = <0x1>;
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xlnx,include-internal-loopback = <0x0>;
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xlnx,include-mdio = <0x1>;
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xlnx,rx-ping-pong = <0x1>;
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xlnx,s-axi-id-width = <0x1>;
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xlnx,tx-ping-pong = <0x1>;
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xlnx,use-internal = <0x0>;
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axi_ethernetlite_0_mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: phy@1 {
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compatible = "ethernet-phy-id001C.C915";
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device_type = "ethernet-phy";
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reg = <1>;
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};
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};
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};
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sdhci_0: sdhci@f000000000 {
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u-boot,dm-spl;
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compatible = "openpiton,piton-mmc", "openpiton,mmc";
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reg = < 0x000000f0 0x00000000 0x00000000 0x00300000 >;
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};
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clint@fff1020000 {
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compatible = "sifive,clint0", "openpiton,clint";
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interrupts-extended = < &CPU0_intc 3
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&CPU0_intc 7
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&CPU1_intc 3
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&CPU1_intc 7 >;
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reg = < 0x000000ff 0xf1020000 0x00000000 0x000c0000 >;
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clocks = <&clk0>;
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};
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PLIC0: plic@fff1100000 {
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u-boot,dm-spl;
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#interrupt-cells = <1>;
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compatible = "sifive,plic-1.0.0", "openpiton,plic";
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interrupt-controller;
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interrupts-extended = < &CPU0_intc 11
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&CPU0_intc 9
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&CPU1_intc 11
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&CPU1_intc 9 >;
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reg = < 0x000000ff 0xf1100000 0x00000000 0x04000000 >;
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riscv,max-priority = <7>;
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riscv,ndev = <2>;
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};
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};
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};
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