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https://github.com/AsahiLinux/u-boot
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9d24274509
Add support for U-BOOT SPL. NOR and RAM mode are supported. There are 3 images in NOR flash. u-boot.img, dtb and kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
188 lines
4.4 KiB
ArmAsm
188 lines
4.4 KiB
ArmAsm
/*
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* (C) Copyright 2007 Michal Simek
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* (C) Copyright 2004 Atmark Techno, Inc.
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*
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* Michal SIMEK <monstr@monstr.eu>
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* Yasushi SHOJI <yashi@atmark-techno.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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.text
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.global _start
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_start:
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/*
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* reserve registers:
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* r10: Stores little/big endian offset for vectors
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* r2: Stores imm opcode
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* r3: Stores brai opcode
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*/
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mts rmsr, r0 /* disable cache */
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#if defined(CONFIG_SPL_BUILD)
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addi r1, r0, CONFIG_SPL_STACK_ADDR
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addi r1, r1, -4 /* Decrement SP to top of memory */
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#else
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addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
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addi r1, r1, -4 /* Decrement SP to top of memory */
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/* Find-out if u-boot is running on BIG/LITTLE endian platform
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* There are some steps which is necessary to keep in mind:
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* 1. Setup offset value to r6
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* 2. Store word offset value to address 0x0
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* 3. Load just byte from address 0x0
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* 4a) LITTLE endian - r10 contains 0x2 because it is the smallest
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* value that's why is on address 0x0
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* 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
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*/
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addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
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lwi r7, r0, 0x28
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swi r6, r0, 0x28 /* used first unused MB vector */
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lbui r10, r0, 0x28 /* used first unused MB vector */
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swi r7, r0, 0x28
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/* add opcode instruction for 32bit jump - 2 instruction imm & brai */
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addi r2, r0, 0xb0000000 /* hex b000 opcode imm */
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addi r3, r0, 0xb8080000 /* hew b808 opcode brai */
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#ifdef CONFIG_SYS_RESET_ADDRESS
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/* reset address */
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swi r2, r0, 0x0 /* reset address - imm opcode */
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swi r3, r0, 0x4 /* reset address - brai opcode */
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addik r6, r0, CONFIG_SYS_RESET_ADDRESS
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x2
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sh r7, r0, r8
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rsubi r8, r10, 0x6
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sh r6, r0, r8
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#endif
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#ifdef CONFIG_SYS_USR_EXCEP
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/* user_vector_exception */
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swi r2, r0, 0x8 /* user vector exception - imm opcode */
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swi r3, r0, 0xC /* user vector exception - brai opcode */
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addik r6, r0, _exception_handler
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sw r6, r1, r0
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/*
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* BIG ENDIAN memory map for user exception
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* 0x8: 0xB000XXXX
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* 0xC: 0xB808XXXX
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*
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* then it is necessary to count address for storing the most significant
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* 16bits from _exception_handler address and copy it to
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* 0xa address. Big endian use offset in r10=0 that's why is it just
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* 0xa address. The same is done for the least significant 16 bits
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* for 0xe address.
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*
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* LITTLE ENDIAN memory map for user exception
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* 0x8: 0xXXXX00B0
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* 0xC: 0xXXXX08B8
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*
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* Offset is for little endian setup to 0x2. rsubi instruction decrease
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* address value to ensure that points to proper place which is
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* 0x8 for the most significant 16 bits and
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* 0xC for the least significant 16 bits
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*/
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lhu r7, r1, r10
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rsubi r8, r10, 0xa
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sh r7, r0, r8
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rsubi r8, r10, 0xe
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sh r6, r0, r8
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#endif
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/* interrupt_handler */
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swi r2, r0, 0x10 /* interrupt - imm opcode */
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swi r3, r0, 0x14 /* interrupt - brai opcode */
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addik r6, r0, _interrupt_handler
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x12
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sh r7, r0, r8
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rsubi r8, r10, 0x16
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sh r6, r0, r8
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/* hardware exception */
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swi r2, r0, 0x20 /* hardware exception - imm opcode */
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swi r3, r0, 0x24 /* hardware exception - brai opcode */
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addik r6, r0, _hw_exception_handler
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x22
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sh r7, r0, r8
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rsubi r8, r10, 0x26
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sh r6, r0, r8
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#endif /* BUILD_SPL */
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/* Flush cache before enable cache */
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addik r5, r0, 0
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addik r6, r0, XILINX_DCACHE_BYTE_SIZE
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flush: bralid r15, flush_cache
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nop
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/* enable instruction and data cache */
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mfs r12, rmsr
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ori r12, r12, 0xa0
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mts rmsr, r12
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clear_bss:
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/* clear BSS segments */
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addi r5, r0, __bss_start
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addi r4, r0, __bss_end
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cmp r6, r5, r4
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beqi r6, 3f
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2:
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swi r0, r5, 0 /* write zero to loc */
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addi r5, r5, 4 /* increment to next loc */
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cmp r6, r5, r4 /* check if we have reach the end */
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bnei r6, 2b
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3: /* jumping to board_init */
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#ifndef CONFIG_SPL_BUILD
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brai board_init_f
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#else
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brai board_init_r
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#endif
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1: bri 1b
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#ifndef CONFIG_SPL_BUILD
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/*
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* Read 16bit little endian
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*/
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.text
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.global in16
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.ent in16
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.align 2
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in16: lhu r3, r0, r5
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bslli r4, r3, 8
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bsrli r3, r3, 8
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andi r4, r4, 0xffff
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or r3, r3, r4
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rtsd r15, 8
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sext16 r3, r3
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.end in16
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/*
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* Write 16bit little endian
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* first parameter(r5) - address, second(r6) - short value
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*/
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.text
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.global out16
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.ent out16
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.align 2
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out16: bslli r3, r6, 8
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bsrli r6, r6, 8
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andi r3, r3, 0xffff
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or r3, r3, r6
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sh r3, r0, r5
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rtsd r15, 8
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or r0, r0, r0
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.end out16
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#endif
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