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https://github.com/AsahiLinux/u-boot
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1eac2a7141
This patch adds support for the Prodrive P3M750 (PPC750 & MV64460) and the P3M7448 (MPC7448 & MV64460) PMC modules. Both modules are quite similar and share the same board directory "prodrive/p3mx" and the same config file "p3mx.h". Signed-off-by: Stefan Roese <sr@denx.de>
245 lines
4.5 KiB
ArmAsm
245 lines
4.5 KiB
ArmAsm
#include <config.h>
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#include <74xx_7xx.h>
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#include "version.h"
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include "../../Marvell/include/mv_gen_reg.h"
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#ifdef CONFIG_ECC
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/* Galileo specific asm code for initializing ECC */
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.globl board_relocate_rom
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board_relocate_rom:
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mflr r7
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/* update the location of the GT registers */
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lis r11, CFG_GT_REGS@h
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/* if we're using ECC, we must use the DMA engine to copy ourselves */
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bl start_idma_transfer_0
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bl wait_for_idma_0
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bl stop_idma_engine_0
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mtlr r7
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blr
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.globl board_init_ecc
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board_init_ecc:
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mflr r7
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/* NOTE: r10 still contains the location we've been relocated to
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* which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
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/* now that we're running from ram, init the rest of main memory
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* for ECC use */
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lis r8, CFG_MONITOR_LEN@h
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ori r8, r8, CFG_MONITOR_LEN@l
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divw r3, r10, r8
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/* set up the counter, and init the starting address */
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mtctr r3
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li r12, 0
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/* bytes per transfer */
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mr r5, r8
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about_to_init_ecc:
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1: mr r3, r12
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mr r4, r12
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bl start_idma_transfer_0
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bl wait_for_idma_0
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bl stop_idma_engine_0
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add r12, r12, r8
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bdnz 1b
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mtlr r7
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blr
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/* r3: dest addr
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* r4: source addr
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* r5: byte count
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* r11: gt regbase
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* trashes: r6, r5
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*/
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start_idma_transfer_0:
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/* set the byte count, including the OWN bit */
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mr r6, r11
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ori r6, r6, CHANNEL0_DMA_BYTE_COUNT
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stwbrx r5, 0, (r6)
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/* set the source address */
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mr r6, r11
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ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
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stwbrx r4, 0, (r6)
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/* set the dest address */
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mr r6, r11
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ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
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stwbrx r3, 0, (r6)
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/* set the next record pointer */
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li r5, 0
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mr r6, r11
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ori r6, r6, CHANNEL0NEXT_RECORD_POINTER
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stwbrx r5, 0, (r6)
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/* set the low control register */
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/* bit 9 is NON chained mode, bit 31 is new style descriptors.
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bit 12 is channel enable */
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ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
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/* 15 shifted by 16 (oris) == bit 31 */
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oris r5, r5, (1 << 15)
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mr r6, r11
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ori r6, r6, CHANNEL0CONTROL
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stwbrx r5, 0, (r6)
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blr
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/* this waits for the bytecount to return to zero, indicating
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* that the trasfer is complete */
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wait_for_idma_0:
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mr r5, r11
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lis r6, 0xff
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ori r6, r6, 0xffff
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ori r5, r5, CHANNEL0_DMA_BYTE_COUNT
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1: lwbrx r4, 0, (r5)
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and. r4, r4, r6
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bne 1b
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blr
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/* this turns off channel 0 of the idma engine */
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stop_idma_engine_0:
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/* shut off the DMA engine */
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li r5, 0
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mr r6, r11
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ori r6, r6, CHANNEL0CONTROL
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stwbrx r5, 0, (r6)
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blr
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#endif
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#ifdef CFG_BOARD_ASM_INIT
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/* NOTE: trashes r3-r7 */
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.globl board_asm_init
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board_asm_init:
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/* just move the GT registers to where they belong */
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lis r3, CFG_DFL_GT_REGS@h
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ori r3, r3, CFG_DFL_GT_REGS@l
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lis r4, CFG_GT_REGS@h
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ori r4, r4, CFG_GT_REGS@l
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li r5, INTERNAL_SPACE_DECODE
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/* test to see if we've already moved */
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lwbrx r6, r5, r4
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andi. r6, r6, 0xffff
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/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
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/* rlwinm r7, r4, 8, 16, 31
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rlwinm r7, r4, 12, 16, 31 */ /* original */
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rlwinm r7, r4, 16, 16, 31
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/* -----------------------------------------------------*/
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cmp cr0, r7, r6
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beqlr
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/* nope, have to move the registers */
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lwbrx r6, r5, r3
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andis. r6, r6, 0xffff
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or r6, r6, r7
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stwbrx r6, r5, r3
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/* now, poll for the change */
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1: lwbrx r7, r5, r4
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cmp cr0, r7, r6
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bne 1b
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lis r3, CFG_INT_SRAM_BASE@h
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ori r3, r3, CFG_INT_SRAM_BASE@l
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rlwinm r3, r3, 16, 16, 31
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lis r4, CFG_GT_REGS@h
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ori r4, r4, CFG_GT_REGS@l
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li r5, INTEGRATED_SRAM_BASE_ADDR
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stwbrx r3, r5, r4
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2: lwbrx r6, r5, r4
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cmp cr0, r3, r6
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bne 2b
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/* done! */
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blr
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#endif
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/* For use of the debug LEDs */
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.global led_on0_relocated
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led_on0_relocated:
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xor r21, r21, r21
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xor r18, r18, r18
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lis r18, 0xFC80
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ori r18, r18, 0x8000
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/* stw r21, 0x0(r18) */
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sync
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blr
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.global led_off0_relocated
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led_off0_relocated:
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xor r21, r21, r21
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xor r18, r18, r18
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lis r18, 0xFC81
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ori r18, r18, 0x4000
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/* stw r21, 0x0(r18) */
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sync
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blr
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.global led_on0
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led_on0:
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xor r18, r18, r18
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lis r18, 0x1c80
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ori r18, r18, 0x8000
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/* stw r18, 0x0(r18) */
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sync
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blr
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.global led_off0
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led_off0:
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xor r18, r18, r18
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lis r18, 0x1c81
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ori r18, r18, 0x4000
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/* stw r18, 0x0(r18) */
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sync
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blr
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.global led_on1
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led_on1:
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xor r18, r18, r18
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lis r18, 0x1c80
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ori r18, r18, 0xc000
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/* stw r18, 0x0(r18) */
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sync
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blr
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.global led_off1
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led_off1:
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xor r18, r18, r18
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lis r18, 0x1c81
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ori r18, r18, 0x8000
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/* stw r18, 0x0(r18) */
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sync
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blr
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.global led_on2
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led_on2:
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xor r18, r18, r18
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lis r18, 0x1c81
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ori r18, r18, 0x0000
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/* stw r18, 0x0(r18) */
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sync
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blr
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.global led_off2
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led_off2:
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xor r18, r18, r18
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lis r18, 0x1c81
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ori r18, r18, 0xc000
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/* stw r18, 0x0(r18) */
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sync
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blr
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