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u-boot/board/freescale/mx53ard
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Troy Kisky 1482410531 MX53: DDR: Fix ZQHWCTRL field TZQ_CS 
Currently, board files are setting this field to 0x01
which the manual says is a reserved value. Change to
use the default of 0x02 - 128 cycles.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-04-16 14:53:58 +02:00
..
imximage_dd3.cfg MX53: DDR: Fix ZQHWCTRL field TZQ_CS 2012-04-16 14:53:58 +02:00
Makefile punt unused clean/distclean targets 2011-10-15 22:20:36 +02:00
mx53ard.c mx53ard: Initialize return code with error 2012-03-27 09:41:17 +02:00