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183f1e2712
The kendryte PLL code uses nop as barrier. The macro is not defined for the sandbox on x86 but is defined on RISC-V. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
62 lines
1.6 KiB
C
62 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
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*/
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#ifndef K210_PLL_H
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#define K210_PLL_H
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#include <clk.h>
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#include <test/export.h>
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#include <asm/io.h>
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#define K210_PLL_CLKR GENMASK(3, 0)
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#define K210_PLL_CLKF GENMASK(9, 4)
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#define K210_PLL_CLKOD GENMASK(13, 10) /* Output Divider */
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#define K210_PLL_BWADJ GENMASK(19, 14) /* BandWidth Adjust */
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#define K210_PLL_RESET BIT(20)
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#define K210_PLL_PWRD BIT(21) /* PoWeReD */
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#define K210_PLL_INTFB BIT(22) /* Internal FeedBack */
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#define K210_PLL_BYPASS BIT(23)
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#define K210_PLL_TEST BIT(24)
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#define K210_PLL_EN BIT(25)
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#define K210_PLL_TEST_EN BIT(26)
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#define K210_PLL_LOCK 0
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#define K210_PLL_CLEAR_SLIP 2
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#define K210_PLL_TEST_OUT 3
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struct k210_pll {
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struct clk clk;
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void __iomem *reg; /* Base PLL register */
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void __iomem *lock; /* Common PLL lock register */
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u8 shift; /* Offset of bits in lock register */
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u8 width; /* Width of lock bits to test against */
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};
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#define to_k210_pll(_clk) container_of(_clk, struct k210_pll, clk)
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struct k210_pll_config {
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u8 r;
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u8 f;
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u8 od;
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};
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#ifdef CONFIG_UNIT_TEST
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TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in,
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struct k210_pll_config *best);
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#ifndef nop
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#define nop()
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#endif
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#endif
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extern const struct clk_ops k210_pll_ops;
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struct clk *k210_register_pll_struct(const char *name, const char *parent_name,
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struct k210_pll *pll);
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struct clk *k210_register_pll(const char *name, const char *parent_name,
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void __iomem *reg, void __iomem *lock, u8 shift,
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u8 width);
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#endif /* K210_PLL_H */
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