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3f123b7424
Add firmware based reset controller for Xilinx ZynqMP SoC to let other drivers to call reset functions. Driver is only tested on Xilinx ZynqMP but support for Xilinx Versal can be simply added. That's why reset_id and nr_reset are assigned in probe folder. Driver is inpired by driver from Linux kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
247 lines
7.2 KiB
C
247 lines
7.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Xilinx Zynq MPSoC Firmware driver
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*
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* Copyright (C) 2018-2019 Xilinx, Inc.
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*/
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#ifndef _ZYNQMP_FIRMWARE_H_
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#define _ZYNQMP_FIRMWARE_H_
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enum pm_api_id {
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PM_GET_API_VERSION = 1,
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PM_SET_CONFIGURATION = 2,
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PM_GET_NODE_STATUS = 3,
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PM_GET_OPERATING_CHARACTERISTIC = 4,
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PM_REGISTER_NOTIFIER = 5,
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/* API for suspending */
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PM_REQUEST_SUSPEND = 6,
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PM_SELF_SUSPEND = 7,
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PM_FORCE_POWERDOWN = 8,
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PM_ABORT_SUSPEND = 9,
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PM_REQUEST_WAKEUP = 10,
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PM_SET_WAKEUP_SOURCE = 11,
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PM_SYSTEM_SHUTDOWN = 12,
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PM_REQUEST_NODE = 13,
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PM_RELEASE_NODE = 14,
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PM_SET_REQUIREMENT = 15,
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PM_SET_MAX_LATENCY = 16,
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/* Direct control API functions: */
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PM_RESET_ASSERT = 17,
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PM_RESET_GET_STATUS = 18,
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PM_MMIO_WRITE = 19,
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PM_MMIO_READ = 20,
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PM_PM_INIT_FINALIZE = 21,
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PM_FPGA_LOAD = 22,
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PM_FPGA_GET_STATUS = 23,
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PM_GET_CHIPID = 24,
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/* ID 25 is been used by U-boot to process secure boot images */
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/* Secure library generic API functions */
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PM_SECURE_SHA = 26,
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PM_SECURE_RSA = 27,
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PM_PINCTRL_REQUEST = 28,
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PM_PINCTRL_RELEASE = 29,
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PM_PINCTRL_GET_FUNCTION = 30,
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PM_PINCTRL_SET_FUNCTION = 31,
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PM_PINCTRL_CONFIG_PARAM_GET = 32,
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PM_PINCTRL_CONFIG_PARAM_SET = 33,
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PM_IOCTL = 34,
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PM_QUERY_DATA = 35,
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PM_CLOCK_ENABLE = 36,
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PM_CLOCK_DISABLE = 37,
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PM_CLOCK_GETSTATE = 38,
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PM_CLOCK_SETDIVIDER = 39,
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PM_CLOCK_GETDIVIDER = 40,
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PM_CLOCK_SETRATE = 41,
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PM_CLOCK_GETRATE = 42,
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PM_CLOCK_SETPARENT = 43,
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PM_CLOCK_GETPARENT = 44,
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PM_SECURE_IMAGE = 45,
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PM_FPGA_READ = 46,
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PM_SECURE_AES = 47,
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PM_CLOCK_PLL_GETPARAM = 49,
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/* PM_REGISTER_ACCESS API */
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PM_REGISTER_ACCESS = 52,
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PM_EFUSE_ACCESS = 53,
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PM_FEATURE_CHECK = 63,
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PM_API_MAX,
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};
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enum pm_query_id {
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PM_QID_INVALID = 0,
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PM_QID_CLOCK_GET_NAME = 1,
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PM_QID_CLOCK_GET_TOPOLOGY = 2,
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PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
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PM_QID_CLOCK_GET_PARENTS = 4,
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PM_QID_CLOCK_GET_ATTRIBUTES = 5,
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PM_QID_PINCTRL_GET_NUM_PINS = 6,
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PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
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PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
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PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
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PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
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PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
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PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
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PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
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};
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enum zynqmp_pm_reset_action {
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PM_RESET_ACTION_RELEASE = 0,
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PM_RESET_ACTION_ASSERT = 1,
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PM_RESET_ACTION_PULSE = 2,
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};
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enum zynqmp_pm_reset {
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ZYNQMP_PM_RESET_START = 1000,
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ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
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ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
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ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
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ZYNQMP_PM_RESET_DP = 1003,
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ZYNQMP_PM_RESET_SWDT_CRF = 1004,
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ZYNQMP_PM_RESET_AFI_FM5 = 1005,
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ZYNQMP_PM_RESET_AFI_FM4 = 1006,
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ZYNQMP_PM_RESET_AFI_FM3 = 1007,
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ZYNQMP_PM_RESET_AFI_FM2 = 1008,
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ZYNQMP_PM_RESET_AFI_FM1 = 1009,
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ZYNQMP_PM_RESET_AFI_FM0 = 1010,
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ZYNQMP_PM_RESET_GDMA = 1011,
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ZYNQMP_PM_RESET_GPU_PP1 = 1012,
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ZYNQMP_PM_RESET_GPU_PP0 = 1013,
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ZYNQMP_PM_RESET_GPU = 1014,
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ZYNQMP_PM_RESET_GT = 1015,
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ZYNQMP_PM_RESET_SATA = 1016,
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ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
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ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
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ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
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ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
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ZYNQMP_PM_RESET_APU_L2 = 1021,
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ZYNQMP_PM_RESET_ACPU3 = 1022,
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ZYNQMP_PM_RESET_ACPU2 = 1023,
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ZYNQMP_PM_RESET_ACPU1 = 1024,
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ZYNQMP_PM_RESET_ACPU0 = 1025,
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ZYNQMP_PM_RESET_DDR = 1026,
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ZYNQMP_PM_RESET_APM_FPD = 1027,
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ZYNQMP_PM_RESET_SOFT = 1028,
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ZYNQMP_PM_RESET_GEM0 = 1029,
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ZYNQMP_PM_RESET_GEM1 = 1030,
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ZYNQMP_PM_RESET_GEM2 = 1031,
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ZYNQMP_PM_RESET_GEM3 = 1032,
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ZYNQMP_PM_RESET_QSPI = 1033,
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ZYNQMP_PM_RESET_UART0 = 1034,
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ZYNQMP_PM_RESET_UART1 = 1035,
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ZYNQMP_PM_RESET_SPI0 = 1036,
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ZYNQMP_PM_RESET_SPI1 = 1037,
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ZYNQMP_PM_RESET_SDIO0 = 1038,
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ZYNQMP_PM_RESET_SDIO1 = 1039,
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ZYNQMP_PM_RESET_CAN0 = 1040,
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ZYNQMP_PM_RESET_CAN1 = 1041,
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ZYNQMP_PM_RESET_I2C0 = 1042,
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ZYNQMP_PM_RESET_I2C1 = 1043,
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ZYNQMP_PM_RESET_TTC0 = 1044,
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ZYNQMP_PM_RESET_TTC1 = 1045,
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ZYNQMP_PM_RESET_TTC2 = 1046,
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ZYNQMP_PM_RESET_TTC3 = 1047,
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ZYNQMP_PM_RESET_SWDT_CRL = 1048,
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ZYNQMP_PM_RESET_NAND = 1049,
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ZYNQMP_PM_RESET_ADMA = 1050,
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ZYNQMP_PM_RESET_GPIO = 1051,
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ZYNQMP_PM_RESET_IOU_CC = 1052,
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ZYNQMP_PM_RESET_TIMESTAMP = 1053,
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ZYNQMP_PM_RESET_RPU_R50 = 1054,
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ZYNQMP_PM_RESET_RPU_R51 = 1055,
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ZYNQMP_PM_RESET_RPU_AMBA = 1056,
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ZYNQMP_PM_RESET_OCM = 1057,
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ZYNQMP_PM_RESET_RPU_PGE = 1058,
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ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
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ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
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ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
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ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
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ZYNQMP_PM_RESET_USB0_APB = 1063,
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ZYNQMP_PM_RESET_USB1_APB = 1064,
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ZYNQMP_PM_RESET_IPI = 1065,
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ZYNQMP_PM_RESET_APM_LPD = 1066,
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ZYNQMP_PM_RESET_RTC = 1067,
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ZYNQMP_PM_RESET_SYSMON = 1068,
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ZYNQMP_PM_RESET_AFI_FM6 = 1069,
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ZYNQMP_PM_RESET_LPD_SWDT = 1070,
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ZYNQMP_PM_RESET_FPD = 1071,
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ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
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ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
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ZYNQMP_PM_RESET_DBG_LPD = 1074,
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ZYNQMP_PM_RESET_DBG_FPD = 1075,
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ZYNQMP_PM_RESET_APLL = 1076,
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ZYNQMP_PM_RESET_DPLL = 1077,
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ZYNQMP_PM_RESET_VPLL = 1078,
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ZYNQMP_PM_RESET_IOPLL = 1079,
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ZYNQMP_PM_RESET_RPLL = 1080,
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ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
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ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
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ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
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ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
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ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
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ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
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ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
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ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
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ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
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ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
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ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
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ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
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ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
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ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
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ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
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ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
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ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
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ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
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ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
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ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
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ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
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ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
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ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
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ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
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ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
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ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
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ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
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ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
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ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
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ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
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ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
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ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
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ZYNQMP_PM_RESET_RPU_LS = 1113,
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ZYNQMP_PM_RESET_PS_ONLY = 1114,
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ZYNQMP_PM_RESET_PL = 1115,
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ZYNQMP_PM_RESET_PS_PL0 = 1116,
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ZYNQMP_PM_RESET_PS_PL1 = 1117,
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ZYNQMP_PM_RESET_PS_PL2 = 1118,
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ZYNQMP_PM_RESET_PS_PL3 = 1119,
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ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
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};
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#define PM_SIP_SVC 0xc2000000
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#define ZYNQMP_PM_VERSION_MAJOR 1
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#define ZYNQMP_PM_VERSION_MINOR 0
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#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
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#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
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#define ZYNQMP_PM_VERSION \
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((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
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ZYNQMP_PM_VERSION_MINOR)
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#define ZYNQMP_PM_VERSION_INVALID ~0
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#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
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/*
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* Return payload size
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* Not every firmware call expects the same amount of return bytes, however the
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* firmware driver always copies 5 bytes from RX buffer to the ret_payload
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* buffer. Therefore allocating with this defined value is recommended to avoid
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* overflows.
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*/
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#define PAYLOAD_ARG_CNT 5U
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unsigned int zynqmp_firmware_version(void);
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void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
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int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
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u32 arg3, u32 *ret_payload);
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#endif /* _ZYNQMP_FIRMWARE_H_ */
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