mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-14 23:33:00 +00:00
fca76cda28
Create *-u-boot.dtsi files for each target dtb of the IOT2050 series so that we can drop the #include deviations from upstream dts[i] files here. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
51 lines
1.2 KiB
Text
51 lines
1.2 KiB
Text
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (c) Siemens AG, 2021
|
|
*
|
|
* Authors:
|
|
* Chao Zeng <chao.zeng@siemens.com>
|
|
* Jan Kiszka <jan.kiszka@siemens.com>
|
|
*
|
|
* Common bits of the IOT2050 Basic and Advanced variants, PG2
|
|
*/
|
|
|
|
&main_pmx0 {
|
|
cp2102n_reset_pin_default: cp2102n-reset-pin-default {
|
|
pinctrl-single,pins = <
|
|
/* (AF12) GPIO1_24, used as cp2102 reset */
|
|
AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7)
|
|
>;
|
|
};
|
|
};
|
|
|
|
&main_gpio1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&cp2102n_reset_pin_default>;
|
|
gpio-line-names =
|
|
"", "", "", "", "", "", "", "", "", "",
|
|
"", "", "", "", "", "", "", "", "", "",
|
|
"", "", "", "", "CP2102N-RESET";
|
|
};
|
|
|
|
&dss {
|
|
/* Workaround needed to get DP clock of 154Mhz */
|
|
assigned-clocks = <&k3_clks 67 0>;
|
|
};
|
|
|
|
&serdes0 {
|
|
assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
|
|
assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
|
|
};
|
|
|
|
&dwc3_0 {
|
|
assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
|
|
<&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
|
|
phys = <&serdes0 PHY_TYPE_USB3 0>;
|
|
phy-names = "usb3-phy";
|
|
};
|
|
|
|
&usb0 {
|
|
maximum-speed = "super-speed";
|
|
snps,dis-u1-entry-quirk;
|
|
snps,dis-u2-entry-quirk;
|
|
};
|