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3ef2412de6
HW coherency won't work properly for CAAM write transactions
if AWCACHE is left to default (POR) value - 4'b0001.
It has to be programmed to 4'b0010.
For platforms that have HW coherency support:
-PPC-based: the update has no effect; CAAM coherency already works
due to the IOMMU (PAMU) driver setting the correct memory coherency
attributes
-ARM-based: the update fixes cache coherency issues,
since IOMMU (SMMU) driver is not programmed to behave similar to PAMU
Fixes:
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.. | ||
desc.h | ||
desc_constr.h | ||
error.c | ||
fsl_blob.c | ||
fsl_hash.c | ||
fsl_hash.h | ||
fsl_rsa.c | ||
jobdesc.c | ||
jobdesc.h | ||
jr.c | ||
jr.h | ||
Kconfig | ||
Makefile | ||
rsa_caam.h | ||
sec.c |