mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 18:28:55 +00:00
c79cbb5952
If for some reason, TSC timer frequency cannot be determined from hardware, nor is it specified in the device tree, U-Boot will panic resulting in endless reset during boot. Let's define a default TSC timer frequency using the Kconfig value CONFIG_X86_TSC_TIMER_FREQ (note: #include must be used instead of /include/ otherwise the macro is not pre-processed). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
94 lines
1.8 KiB
Text
94 lines
1.8 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-router/intel-irq.h>
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/* ICH9 IRQ router has discrete PIRQ control registers */
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#undef PIRQE
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#undef PIRQF
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#undef PIRQG
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#undef PIRQH
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#define PIRQE 8
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#define PIRQF 9
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#define PIRQG 10
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#define PIRQH 11
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/include/ "skeleton.dtsi"
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/include/ "serial.dtsi"
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/include/ "keyboard.dtsi"
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/include/ "reset.dtsi"
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/include/ "rtc.dtsi"
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#include "tsc_timer.dtsi"
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#include "smbios.dtsi"
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/ {
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model = "QEMU x86 (Q35)";
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compatible = "qemu,x86";
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config {
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silent_console = <0>;
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u-boot,no-apm-finalize;
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};
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chosen {
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stdout-path = "/serial";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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u-boot,dm-pre-reloc;
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cpu@0 {
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device_type = "cpu";
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compatible = "cpu-qemu";
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u-boot,dm-pre-reloc;
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reg = <0>;
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intel,apic-id = <0>;
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};
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};
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pci {
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compatible = "pci-x86";
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#address-cells = <3>;
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#size-cells = <2>;
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u-boot,dm-pre-reloc;
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ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
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0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
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0x01000000 0x0 0x2000 0x2000 0 0xe000>;
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pch@1f,0 {
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reg = <0x0000f800 0 0 0 0>;
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compatible = "intel,pch9";
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u-boot,dm-pre-reloc;
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irq-router {
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compatible = "intel,irq-router";
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u-boot,dm-pre-reloc;
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intel,pirq-config = "pci";
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intel,actl-8bit;
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intel,actl-addr = <0x44>;
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intel,pirq-link = <0x60 8>;
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intel,pirq-mask = <0x0e40>;
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intel,pirq-routing = <
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/* e1000 NIC */
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PCI_BDF(0, 2, 0) INTA PIRQG
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/* ICH9 UHCI */
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PCI_BDF(0, 29, 0) INTA PIRQA
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PCI_BDF(0, 29, 1) INTB PIRQB
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PCI_BDF(0, 29, 2) INTC PIRQC
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/* ICH9 EHCI */
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PCI_BDF(0, 29, 7) INTD PIRQD
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/* ICH9 SATA */
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PCI_BDF(0, 31, 2) INTA PIRQA
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>;
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};
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};
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};
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};
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