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https://github.com/AsahiLinux/u-boot
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This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
69 lines
2.9 KiB
Text
69 lines
2.9 KiB
Text
U-boot for arm64
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Summary
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=======
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No hardware platform of arm64 is available now. The u-boot is
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simulated on Foundation Model and Fast Model for ARMv8.
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Notes
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=====
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1. Currenly, u-boot run at the highest exception level processor
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supported and jump to EL2 or optionally EL1 before enter OS.
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2. U-boot for arm64 is compiled with AArch64-gcc. AArch64-gcc
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use rela relocation format, a tool(tools/relocate-rela) by Scott Wood
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is used to encode the initial addend of rela to u-boot.bin. After running,
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the u-boot will be relocated to destination again.
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3. Fdt should be placed at a 2-megabyte boundary and within the first 512
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megabytes from the start of the kernel image. So, fdt_high should be
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defined specially.
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Please reference linux/Documentation/arm64/booting.txt for detail.
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4. Spin-table is used to wake up secondary processors. One location
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(or per processor location) is defined to hold the kernel entry point
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for secondary processors. It must be ensured that the location is
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accessible and zero immediately after secondary processor
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enter slave_cpu branch execution in start.S. The location address
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is encoded in cpu node of DTS. Linux kernel store the entry point
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of secondary processors to it and send event to wakeup secondary
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processors.
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Please reference linux/Documentation/arm64/booting.txt for detail.
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5. Generic board is supported.
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6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and
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aarch32 specific codes.
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7. CONFIG_SYS_FULL_VA is used to enable 2-level page tables. For cores
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supporting 64k pages it allows usage of full 48+ virtual/physical addresses
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Enabling this option requires the following ones to be defined:
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- CONFIG_SYS_MEM_MAP - an array of 'struct mm_region' describing the
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system memory map (start, length, attributes)
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- CONFIG_SYS_MEM_MAP_SIZE - number of entries in CONFIG_SYS_MEM_MAP
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- CONFIG_SYS_PTL1_ENTRIES - number of 1st level page table entries
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- CONFIG_SYS_PTL2_ENTRIES - number of 1nd level page table entries
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for the largest CONFIG_SYS_MEM_MAP entry
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- CONFIG_COREID_MASK - the mask value used to get the core from the
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MPIDR_EL1 register
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- CONFIG_SYS_PTL2_BITS - number of bits addressed by the 2nd level
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page tables
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- CONFIG_SYS_BLOCK_SHIFT - number of bits addressed by a single block
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entry from L2 page tables
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- CONFIG_SYS_PGTABLE_SIZE - total size of the page table
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- CONFIG_SYS_TCR_EL{1,2,3}_IPS_BITS - the IPS field of the TCR_EL{1,2,3}
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Contributor
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===========
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Tom Rini <trini@ti.com>
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Scott Wood <scottwood@freescale.com>
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York Sun <yorksun@freescale.com>
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Simon Glass <sjg@chromium.org>
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Sharma Bhupesh <bhupesh.sharma@freescale.com>
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Rob Herring <robherring2@gmail.com>
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Sergey Temerkhanov <s.temerkhanov@gmail.com>
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