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3ecec5aadd
Add PWM definition to sun50i-a64.dtsi Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
458 lines
12 KiB
Text
458 lines
12 KiB
Text
/*
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* Copyright (C) 2016 ARM Ltd.
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* based on the Allwinner H3 dtsi:
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* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/sun50i-a64-ccu.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/sun50i-a64-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <3>;
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enable-method = "psci";
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};
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};
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osc24M: osc24M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: osc32k_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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iosc: internal-osc-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <16000000>;
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clock-accuracy = <300000000>;
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clock-output-names = "iosc";
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun50i-a64-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC0>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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max-frequency = <150000000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@1c10000 {
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compatible = "allwinner,sun50i-a64-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC1>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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max-frequency = <150000000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@1c11000 {
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compatible = "allwinner,sun50i-a64-emmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC2>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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max-frequency = <200000000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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usb_otg: usb@01c19000 {
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compatible = "allwinner,sun8i-a33-musb";
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reg = <0x01c19000 0x0400>;
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clocks = <&ccu CLK_BUS_OTG>;
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resets = <&ccu RST_BUS_OTG>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mc";
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phys = <&usbphy 0>;
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phy-names = "usb";
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extcon = <&usbphy 0>;
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status = "disabled";
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};
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usbphy: phy@01c19400 {
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compatible = "allwinner,sun50i-a64-usb-phy";
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reg = <0x01c19400 0x14>,
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<0x01c1a800 0x4>,
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<0x01c1b800 0x4>;
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reg-names = "phy_ctrl",
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"pmu0",
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"pmu1";
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clocks = <&ccu CLK_USB_PHY0>,
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<&ccu CLK_USB_PHY1>;
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clock-names = "usb0_phy",
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"usb1_phy";
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resets = <&ccu RST_USB_PHY0>,
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<&ccu RST_USB_PHY1>;
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reset-names = "usb0_reset",
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"usb1_reset";
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status = "disabled";
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#phy-cells = <1>;
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};
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ehci0: usb@01c1a000 {
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compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
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reg = <0x01c1a000 0x100>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_OHCI0>,
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<&ccu CLK_BUS_EHCI0>,
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<&ccu CLK_USB_OHCI0>;
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resets = <&ccu RST_BUS_OHCI0>,
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<&ccu RST_BUS_EHCI0>;
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status = "disabled";
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};
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ohci0: usb@01c1a400 {
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compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
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reg = <0x01c1a400 0x100>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_OHCI0>,
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<&ccu CLK_USB_OHCI0>;
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resets = <&ccu RST_BUS_OHCI0>;
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status = "disabled";
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};
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ehci1: usb@01c1b000 {
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compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
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reg = <0x01c1b000 0x100>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_OHCI1>,
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<&ccu CLK_BUS_EHCI1>,
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<&ccu CLK_USB_OHCI1>;
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resets = <&ccu RST_BUS_OHCI1>,
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<&ccu RST_BUS_EHCI1>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci1: usb@01c1b400 {
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compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
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reg = <0x01c1b400 0x100>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_OHCI1>,
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<&ccu CLK_USB_OHCI1>;
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resets = <&ccu RST_BUS_OHCI1>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ccu: clock@01c20000 {
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compatible = "allwinner,sun50i-a64-ccu";
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reg = <0x01c20000 0x400>;
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clocks = <&osc24M>, <&osc32k>;
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clock-names = "hosc", "losc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pio: pinctrl@1c20800 {
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compatible = "allwinner,sun50i-a64-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu 58>;
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <3>;
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i2c1_pins: i2c1_pins {
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pins = "PH2", "PH3";
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function = "i2c1";
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};
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mmc0_pins: mmc0-pins {
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pins = "PF0", "PF1", "PF2", "PF3",
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"PF4", "PF5";
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function = "mmc0";
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drive-strength = <30>;
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bias-pull-up;
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};
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mmc1_pins: mmc1-pins {
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pins = "PG0", "PG1", "PG2", "PG3",
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"PG4", "PG5";
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function = "mmc1";
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drive-strength = <30>;
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bias-pull-up;
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};
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mmc2_pins: mmc2-pins {
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pins = "PC1", "PC5", "PC6", "PC8", "PC9",
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"PC10","PC11", "PC12", "PC13",
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"PC14", "PC15", "PC16";
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function = "mmc2";
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drive-strength = <30>;
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bias-pull-up;
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};
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uart0_pins_a: uart0@0 {
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pins = "PB8", "PB9";
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function = "uart0";
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};
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uart1_pins: uart1_pins {
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pins = "PG6", "PG7";
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function = "uart1";
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};
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uart1_rts_cts_pins: uart1_rts_cts_pins {
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pins = "PG8", "PG9";
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function = "uart1";
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};
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};
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pwm: pwm@01c21400 {
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compatible = "allwinner,sun50i-a64-pwm",
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"allwinner,sun5i-a13-pwm";
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reg = <0x01c21400 0x8>;
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clocks = <&osc24M>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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uart0: serial@1c28000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28000 0x400>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu 67>;
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resets = <&ccu 46>;
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status = "disabled";
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};
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uart1: serial@1c28400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28400 0x400>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu 68>;
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resets = <&ccu 47>;
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status = "disabled";
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};
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uart2: serial@1c28800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28800 0x400>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu 69>;
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resets = <&ccu 48>;
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status = "disabled";
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};
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uart3: serial@1c28c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28c00 0x400>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu 70>;
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resets = <&ccu 49>;
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status = "disabled";
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};
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uart4: serial@1c29000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29000 0x400>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu 71>;
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resets = <&ccu 50>;
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status = "disabled";
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};
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i2c0: i2c@1c2ac00 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2ac00 0x400>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu 63>;
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resets = <&ccu 42>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c1: i2c@1c2b000 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2b000 0x400>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu 64>;
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resets = <&ccu 43>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c2: i2c@1c2b400 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2b400 0x400>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu 65>;
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resets = <&ccu 44>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gic: interrupt-controller@1c81000 {
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compatible = "arm,gic-400";
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reg = <0x01c81000 0x1000>,
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<0x01c82000 0x2000>,
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<0x01c84000 0x2000>,
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<0x01c86000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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rtc: rtc@1f00000 {
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compatible = "allwinner,sun6i-a31-rtc";
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reg = <0x01f00000 0x54>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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};
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r_ccu: clock@1f01400 {
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compatible = "allwinner,sun50i-a64-r-ccu";
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reg = <0x01f01400 0x100>;
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clocks = <&osc24M>, <&osc32k>, <&iosc>;
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clock-names = "hosc", "losc", "iosc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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r_pio: pinctrl@01f02c00 {
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compatible = "allwinner,sun50i-a64-r-pinctrl";
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reg = <0x01f02c00 0x400>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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};
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};
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