mirror of
https://github.com/AsahiLinux/u-boot
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8e0df066ff
Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
45 lines
966 B
C
45 lines
966 B
C
/*
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* Copyright (c) 2014 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _post_h
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#define _post_h
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/* port to use for post codes */
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#define POST_PORT 0x80
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/* post codes which represent various stages of init */
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#define POST_START 0x1e
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#define POST_CAR_START 0x1f
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#define POST_CAR_SIPI 0x20
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#define POST_CAR_MTRR 0x21
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#define POST_CAR_UNCACHEABLE 0x22
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#define POST_CAR_BASE_ADDRESS 0x23
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#define POST_CAR_MASK 0x24
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#define POST_CAR_FILL 0x25
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#define POST_CAR_ROM_CACHE 0x26
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#define POST_CAR_MRC_CACHE 0x27
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#define POST_CAR_CPU_CACHE 0x28
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#define POST_START_STACK 0x29
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#define POST_START_DONE 0x2a
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#define POST_CPU_INIT 0x2b
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#define POST_EARLY_INIT 0x2c
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#define POST_CPU_INFO 0x2d
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/* Output a post code using al - value must be 0 to 0xff */
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#ifdef __ASSEMBLY__
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#define post_code(value) \
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movb $value, %al; \
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outb %al, $POST_PORT
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#else
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#include <asm/io.h>
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static inline void post_code(int code)
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{
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outb(code, POST_PORT);
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}
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#endif
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#endif
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