mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-19 03:08:31 +00:00
c837dcb1a3
before we can access it; add delay in case we are faster (with no CF card inserted) * Cleanup of some init functions * Make sure SCC Ethernet is always stopped by the time we boot Linux to avoid Linux crashes by early packets coming in. * Accelerate flash accesses on LWMON board by using buffered writes
155 lines
5.5 KiB
C
155 lines
5.5 KiB
C
#ifndef __LINUX_PS2MULT_H
|
|
#define __LINUX_PS2MULT_H
|
|
|
|
#define kbd_request_region() ps2mult_init()
|
|
#define kbd_request_irq(handler) ps2mult_request_irq(handler)
|
|
|
|
#define kbd_read_input() ps2mult_read_input()
|
|
#define kbd_read_status() ps2mult_read_status()
|
|
#define kbd_write_output(val) ps2mult_write_output(val)
|
|
#define kbd_write_command(val) ps2mult_write_command(val)
|
|
|
|
#define aux_request_irq(hand, dev_id) 0
|
|
#define aux_free_irq(dev_id)
|
|
|
|
#define PS2MULT_KB_SELECTOR 0xA0
|
|
#define PS2MULT_MS_SELECTOR 0xA1
|
|
#define PS2MULT_ESCAPE 0x7D
|
|
#define PS2MULT_BSYNC 0x7E
|
|
#define PS2MULT_SESSION_START 0x55
|
|
#define PS2MULT_SESSION_END 0x56
|
|
|
|
#define PS2BUF_SIZE 512 /* power of 2, please */
|
|
|
|
#ifndef CONFIG_PS2MULT_DELAY
|
|
#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
|
|
#endif
|
|
|
|
/* PS/2 controller interface (include/asm/keyboard.h)
|
|
*/
|
|
extern int ps2mult_init (void);
|
|
extern int ps2mult_request_irq(void (*handler)(void *));
|
|
extern u_char ps2mult_read_input(void);
|
|
extern u_char ps2mult_read_status(void);
|
|
extern void ps2mult_write_output(u_char val);
|
|
extern void ps2mult_write_command(u_char val);
|
|
|
|
extern void ps2mult_early_init (void);
|
|
extern void ps2mult_callback (int in_cnt);
|
|
|
|
/* Simple serial interface
|
|
*/
|
|
extern int ps2ser_init(void);
|
|
extern void ps2ser_putc(int chr);
|
|
extern int ps2ser_getc(void);
|
|
extern int ps2ser_check(void);
|
|
|
|
|
|
/* Serial related stuff
|
|
*/
|
|
struct serial_state {
|
|
int baud_base;
|
|
int irq;
|
|
u8 *iomem_base;
|
|
};
|
|
|
|
#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
|
|
#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
|
|
#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
|
|
|
|
#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
|
|
#define UART_IER 1 /* Out: Interrupt Enable Register */
|
|
|
|
#define UART_IIR 2 /* In: Interrupt ID Register */
|
|
#define UART_FCR 2 /* Out: FIFO Control Register */
|
|
|
|
#define UART_LCR 3 /* Out: Line Control Register */
|
|
#define UART_MCR 4 /* Out: Modem Control Register */
|
|
#define UART_LSR 5 /* In: Line Status Register */
|
|
#define UART_MSR 6 /* In: Modem Status Register */
|
|
#define UART_SCR 7 /* I/O: Scratch Register */
|
|
|
|
/*
|
|
* These are the definitions for the FIFO Control Register
|
|
* (16650 only)
|
|
*/
|
|
#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
|
|
#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
|
|
#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
|
|
#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
|
|
#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
|
|
#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
|
|
#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
|
|
#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
|
|
#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
|
|
|
|
/*
|
|
* These are the definitions for the Line Control Register
|
|
*
|
|
* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
|
|
* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
|
|
*/
|
|
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
|
|
#define UART_LCR_SBC 0x40 /* Set break control */
|
|
#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
|
|
#define UART_LCR_EPAR 0x10 /* Even parity select */
|
|
#define UART_LCR_PARITY 0x08 /* Parity Enable */
|
|
#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
|
|
#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
|
|
#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
|
|
#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
|
|
#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
|
|
|
|
/*
|
|
* These are the definitions for the Line Status Register
|
|
*/
|
|
#define UART_LSR_TEMT 0x40 /* Transmitter empty */
|
|
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
|
|
#define UART_LSR_BI 0x10 /* Break interrupt indicator */
|
|
#define UART_LSR_FE 0x08 /* Frame error indicator */
|
|
#define UART_LSR_PE 0x04 /* Parity error indicator */
|
|
#define UART_LSR_OE 0x02 /* Overrun error indicator */
|
|
#define UART_LSR_DR 0x01 /* Receiver data ready */
|
|
|
|
/*
|
|
* These are the definitions for the Interrupt Identification Register
|
|
*/
|
|
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
|
|
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
|
|
|
|
#define UART_IIR_MSI 0x00 /* Modem status interrupt */
|
|
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
|
|
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
|
|
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
|
|
|
|
/*
|
|
* These are the definitions for the Interrupt Enable Register
|
|
*/
|
|
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
|
|
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
|
|
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
|
|
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
|
|
|
|
/*
|
|
* These are the definitions for the Modem Control Register
|
|
*/
|
|
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
|
|
#define UART_MCR_OUT2 0x08 /* Out2 complement */
|
|
#define UART_MCR_OUT1 0x04 /* Out1 complement */
|
|
#define UART_MCR_RTS 0x02 /* RTS complement */
|
|
#define UART_MCR_DTR 0x01 /* DTR complement */
|
|
|
|
/*
|
|
* These are the definitions for the Modem Status Register
|
|
*/
|
|
#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
|
|
#define UART_MSR_RI 0x40 /* Ring Indicator */
|
|
#define UART_MSR_DSR 0x20 /* Data Set Ready */
|
|
#define UART_MSR_CTS 0x10 /* Clear to Send */
|
|
#define UART_MSR_DDCD 0x08 /* Delta DCD */
|
|
#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
|
|
#define UART_MSR_DDSR 0x02 /* Delta DSR */
|
|
#define UART_MSR_DCTS 0x01 /* Delta CTS */
|
|
#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
|
|
|
|
#endif /* __LINUX_PS2MULT_H */
|