mirror of
https://github.com/AsahiLinux/u-boot
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358 lines
12 KiB
C
358 lines
12 KiB
C
/*
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* m520x.h -- Definitions for Freescale Coldfire 520x
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*
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* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __M520X__
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#define __M520X__
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/* *** System Control Module (SCM) *** */
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#define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28)
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#define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24)
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#define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20)
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#define MPROT_MTR 4
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#define MPROT_MTW 2
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#define MPROT_MPL 1
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#define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28)
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#define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24)
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#define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20)
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#define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12)
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#define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28)
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#define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24)
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#define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20)
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#define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8)
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#define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4)
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#define SCM_PACRC_PACR23(x) ((x) & 0x0F)
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#define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28)
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#define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24)
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#define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20)
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#define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12)
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#define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8)
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#define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4)
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#define SCM_PACRD_PACR31(x) ((x) & 0x0F)
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#define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28)
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#define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24)
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#define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20)
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#define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16)
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#define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12)
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#define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28)
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#define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24)
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#define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20)
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#define PACR_SP 4
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#define PACR_WP 2
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#define PACR_TP 1
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#define SCM_BMT_BME (0x00000008)
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#define SCM_BMT_BMT_MASK (0x07)
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#define SCM_BMT_BMT(x) ((x) & 0x07)
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#define SCM_BMT_BMT1024 (0x0000)
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#define SCM_BMT_BMT512 (0x0001)
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#define SCM_BMT_BMT256 (0x0002)
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#define SCM_BMT_BMT128 (0x0003)
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#define SCM_BMT_BMT64 (0x0004)
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#define SCM_BMT_BMT32 (0x0005)
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#define SCM_BMT_BMT16 (0x0006)
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#define SCM_BMT_BMT8 (0x0007)
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#define SCM_CWCR_RO (0x8000)
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#define SCM_CWCR_CWR_WH (0x0100)
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#define SCM_CWCR_CWE (0x0080)
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#define SCM_CWRI_WINDOW (0x0060)
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#define SCM_CWRI_RESET (0x0040)
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#define SCM_CWRI_INT_RESET (0x0020)
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#define SCM_CWRI_INT (0x0000)
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#define SCM_CWCR_CWT(x) (((x) & 0x001F))
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#define SCM_ISR_CFEI (0x02)
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#define SCM_ISR_CWIC (0x01)
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#define SCM_CFIER_ECFEI (0x01)
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#define SCM_CFLOC_LOC (0x80)
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#define SCM_CFATR_WRITE (0x80)
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#define SCM_CFATR_SZ32 (0x20)
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#define SCM_CFATR_SZ16 (0x10)
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#define SCM_CFATR_SZ08 (0x00)
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#define SCM_CFATR_CACHE (0x08)
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#define SCM_CFATR_MODE (0x02)
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#define SCM_CFATR_TYPE (0x01)
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/* *** Interrupt Controller (INTC) *** */
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#define INT0_LO_RSVD0 (0)
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#define INT0_LO_EPORT_F1 (1)
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#define INT0_LO_EPORT_F4 (2)
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#define INT0_LO_EPORT_F7 (3)
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#define INT1_LO_PIT0 (4)
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#define INT1_LO_PIT1 (5)
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/* 6 - 7 rsvd */
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#define INT0_LO_EDMA_00 (8)
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#define INT0_LO_EDMA_01 (9)
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#define INT0_LO_EDMA_02 (10)
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#define INT0_LO_EDMA_03 (11)
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#define INT0_LO_EDMA_04 (12)
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#define INT0_LO_EDMA_05 (13)
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#define INT0_LO_EDMA_06 (14)
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#define INT0_LO_EDMA_07 (15)
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#define INT0_LO_EDMA_08 (16)
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#define INT0_LO_EDMA_09 (17)
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#define INT0_LO_EDMA_10 (18)
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#define INT0_LO_EDMA_11 (19)
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#define INT0_LO_EDMA_12 (20)
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#define INT0_LO_EDMA_13 (21)
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#define INT0_LO_EDMA_14 (22)
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#define INT0_LO_EDMA_15 (23)
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#define INT0_LO_EDMA_ERR (24)
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#define INT0_LO_SCM_CWIC (25)
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#define INT0_LO_UART0 (26)
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#define INT0_LO_UART1 (27)
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#define INT0_LO_UART2 (28)
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/* 29 rsvd */
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#define INT0_LO_I2C (30)
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#define INT0_LO_QSPI (31)
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#define INT0_HI_DTMR0 (32)
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#define INT0_HI_DTMR1 (33)
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#define INT0_HI_DTMR2 (34)
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#define INT0_HI_DTMR3 (35)
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#define INT0_HI_FEC0_TXF (36)
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#define INT0_HI_FEC0_TXB (37)
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#define INT0_HI_FEC0_UN (38)
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#define INT0_HI_FEC0_RL (39)
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#define INT0_HI_FEC0_RXF (40)
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#define INT0_HI_FEC0_RXB (41)
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#define INT0_HI_FEC0_MII (42)
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#define INT0_HI_FEC0_LC (43)
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#define INT0_HI_FEC0_HBERR (44)
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#define INT0_HI_FEC0_GRA (45)
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#define INT0_HI_FEC0_EBERR (46)
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#define INT0_HI_FEC0_BABT (47)
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#define INT0_HI_FEC0_BABR (48)
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/* 49 - 61 rsvd */
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#define INT0_HI_SCMISR_CFEI (62)
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/* *** Reset Controller Module (RCM) *** */
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#define RCM_RCR_SOFTRST (0x80)
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#define RCM_RCR_FRCRSTOUT (0x40)
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#define RCM_RSR_SOFT (0x20)
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#define RCM_RSR_WDOG (0x10)
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#define RCM_RSR_POR (0x08)
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#define RCM_RSR_EXT (0x04)
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#define RCM_RSR_WDR_CORE (0x02)
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#define RCM_RSR_LOL (0x01)
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/* *** Chip Configuration Module (CCM) *** */
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#define CCM_CCR_CSC (0x0200)
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#define CCM_CCR_OSCFREQ (0x0080)
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#define CCM_CCR_LIMP (0x0040)
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#define CCM_CCR_LOAD (0x0020)
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#define CCM_CCR_BOOTPS(x) (((x) & 0x0003) << 3)
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#define CCM_CCR_OSC_MODE (0x0004)
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#define CCM_CCR_PLL_MODE (0x0002)
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#define CCM_CCR_RESERVED (0x0001)
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#define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6)
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#define CCM_CIR_PRN(x) ((x) & 0x003F)
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/* *** General Purpose I/O (GPIO) *** */
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#define GPIO_PDR_BUSCTL(x) ((x) & 0x0F)
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#define GPIO_PDR_BE(x) ((x) & 0x0F)
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#define GPIO_PDR_CS(x) (((x) & 0x07) << 1)
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#define GPIO_PDR_FECI2C(x) ((x) & 0x0F)
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#define GPIO_PDR_QSPI(x) ((x) & 0x0F)
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#define GPIO_PDR_TIMER(x) ((x) & 0x0F)
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#define GPIO_PDR_UART(x) ((x) & 0xFF)
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#define GPIO_PDR_FECH(x) ((x) & 0xFF)
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#define GPIO_PDR_FECL(x) ((x) & 0xFF)
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#define GPIO_PAR_FBCTL_OE (0x10)
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#define GPIO_PAR_FBCTL_TA (0x08)
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#define GPIO_PAR_FBCTL_RWB (0x04)
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#define GPIO_PAR_FBCTL_TS_MASK (0xFC)
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#define GPIO_PAR_FBCTL_TS_TS (0x03)
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#define GPIO_PAR_FBCTL_TS_DMA (0x02)
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#define GPIO_PAR_BE3 (0x08)
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#define GPIO_PAR_BE2 (0x04)
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#define GPIO_PAR_BE1 (0x02)
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#define GPIO_PAR_BE0 (0x01)
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#define GPIO_PAR_CS3 (0x08)
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#define GPIO_PAR_CS2 (0x04)
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#define GPIO_PAR_CS1_MASK (0xFC)
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#define GPIO_PAR_CS1_CS1 (0x03)
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#define GPIO_PAR_CS1_SDCS1 (0x02)
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#define GPIO_PAR_FECI2C_RMII_MASK (0x0F)
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#define GPIO_PAR_FECI2C_MDC_MASK (0x3F)
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#define GPIO_PAR_FECI2C_MDC_MDC (0xC0)
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#define GPIO_PAR_FECI2C_MDC_SCL (0x80)
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#define GPIO_PAR_FECI2C_MDC_U2TXD (0x40)
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#define GPIO_PAR_FECI2C_MDIO_MASK (0xCF)
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#define GPIO_PAR_FECI2C_MDIO_MDIO (0x30)
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#define GPIO_PAR_FECI2C_MDIO_SDA (0x20)
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#define GPIO_PAR_FECI2C_MDIO_U2RXD (0x10)
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#define GPIO_PAR_FECI2C_I2C_MASK (0xF0)
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#define GPIO_PAR_FECI2C_SCL_MASK (0xF3)
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#define GPIO_PAR_FECI2C_SCL_SCL (0x0C)
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#define GPIO_PAR_FECI2C_SCL_U2RXD (0x04)
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#define GPIO_PAR_FECI2C_SDA_MASK (0xFC)
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#define GPIO_PAR_FECI2C_SDA_SDA (0x03)
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#define GPIO_PAR_FECI2C_SDA_U2TXD (0x01)
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#define GPIO_PAR_QSPI_PCS2_MASK (0x3F)
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#define GPIO_PAR_QSPI_PCS2_PCS2 (0xC0)
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#define GPIO_PAR_QSPI_PCS2_DACK0 (0x80)
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#define GPIO_PAR_QSPI_PCS2_U2RTS (0x40)
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#define GPIO_PAR_QSPI_DIN_MASK (0xCF)
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#define GPIO_PAR_QSPI_DIN_DIN (0x30)
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#define GPIO_PAR_QSPI_DIN_DREQ0 (0x20)
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#define GPIO_PAR_QSPI_DIN_U2CTS (0x10)
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#define GPIO_PAR_QSPI_DOUT_MASK (0xF3)
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#define GPIO_PAR_QSPI_DOUT_DOUT (0x0C)
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#define GPIO_PAR_QSPI_DOUT_SDA (0x08)
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#define GPIO_PAR_QSPI_SCK_MASK (0xFC)
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#define GPIO_PAR_QSPI_SCK_SCK (0x03)
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#define GPIO_PAR_QSPI_SCK_SCL (0x02)
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#define GPIO_PAR_TMR_TIN3(x) (((x) & 0x03) << 6)
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#define GPIO_PAR_TMR_TIN2(x) (((x) & 0x03) << 4)
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#define GPIO_PAR_TMR_TIN1(x) (((x) & 0x03) << 2)
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#define GPIO_PAR_TMR_TIN0(x) ((x) & 0x03)
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#define GPIO_PAR_TMR_TIN3_MASK (0x3F)
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#define GPIO_PAR_TMR_TIN3_TIN3 (0xC0)
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#define GPIO_PAR_TMR_TIN3_TOUT3 (0x80)
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#define GPIO_PAR_TMR_TIN3_U2CTS (0x40)
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#define GPIO_PAR_TMR_TIN2_MASK (0xCF)
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#define GPIO_PAR_TMR_TIN2_TIN2 (0x30)
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#define GPIO_PAR_TMR_TIN2_TOUT2 (0x20)
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#define GPIO_PAR_TMR_TIN2_U2RTS (0x10)
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#define GPIO_PAR_TMR_TIN1_MASK (0xF3)
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#define GPIO_PAR_TMR_TIN1_TIN1 (0x0C)
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#define GPIO_PAR_TMR_TIN1_TOUT1 (0x08)
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#define GPIO_PAR_TMR_TIN1_U2RXD (0x04)
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#define GPIO_PAR_TMR_TIN0_MASK (0xFC)
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#define GPIO_PAR_TMR_TIN0_TIN0 (0x03)
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#define GPIO_PAR_TMR_TIN0_TOUT0 (0x02)
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#define GPIO_PAR_TMR_TIN0_U2TXD (0x01)
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#define GPIO_PAR_UART1_MASK (0xF03F)
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#define GPIO_PAR_UART0_MASK (0xFFC0)
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#define GPIO_PAR_UART_U1CTS_MASK (0xF3FF)
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#define GPIO_PAR_UART_U1CTS_U1CTS (0x0C00)
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#define GPIO_PAR_UART_U1CTS_TIN1 (0x0800)
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#define GPIO_PAR_UART_U1CTS_PCS1 (0x0400)
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#define GPIO_PAR_UART_U1RTS_MASK (0xFCFF)
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#define GPIO_PAR_UART_U1RTS_U1RTS (0x0300)
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#define GPIO_PAR_UART_U1RTS_TOUT1 (0x0200)
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#define GPIO_PAR_UART_U1RTS_PCS1 (0x0100)
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#define GPIO_PAR_UART_U1TXD (0x0080)
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#define GPIO_PAR_UART_U1RXD (0x0040)
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#define GPIO_PAR_UART_U0CTS_MASK (0xFFCF)
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#define GPIO_PAR_UART_U0CTS_U0CTS (0x0030)
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#define GPIO_PAR_UART_U0CTS_TIN0 (0x0020)
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#define GPIO_PAR_UART_U0CTS_PCS0 (0x0010)
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#define GPIO_PAR_UART_U0RTS_MASK (0xFFF3)
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#define GPIO_PAR_UART_U0RTS_U0RTS (0x000C)
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#define GPIO_PAR_UART_U0RTS_TOUT0 (0x0008)
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#define GPIO_PAR_UART_U0RTS_PCS0 (0x0004)
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#define GPIO_PAR_UART_U0TXD (0x0002)
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#define GPIO_PAR_UART_U0RXD (0x0001)
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#define GPIO_PAR_FEC_7W_MASK (0xF3)
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#define GPIO_PAR_FEC_7W_FEC (0x0C)
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#define GPIO_PAR_FEC_7W_U1RTS (0x04)
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#define GPIO_PAR_FEC_MII_MASK (0xFC)
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#define GPIO_PAR_FEC_MII_FEC (0x03)
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#define GPIO_PAR_FEC_MII_UnCTS (0x01)
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#define GPIO_PAR_IRQ_IRQ4 (0x01)
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#define GPIO_MSCR_FB_FBCLK(x) (((x) & 0x03) << 6)
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#define GPIO_MSCR_FB_DUP(x) (((x) & 0x03) << 4)
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#define GPIO_MSCR_FB_DLO(x) (((x) & 0x03) << 2)
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#define GPIO_MSCR_FB_ADRCTL(x) ((x) & 0x03)
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#define GPIO_MSCR_FB_FBCLK_MASK (0x3F)
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#define GPIO_MSCR_FB_DUP_MASK (0xCF)
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#define GPIO_MSCR_FB_DLO_MASK (0xF3)
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#define GPIO_MSCR_FB_ADRCTL_MASK (0xFC)
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#define GPIO_MSCR_SDR_SDCLKB(x) (((x) & 0x03) << 4)
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#define GPIO_MSCR_SDR_SDCLK(x) (((x) & 0x03) << 2)
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#define GPIO_MSCR_SDR_SDRAM(x) ((x) & 0x03)
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#define GPIO_MSCR_SDR_SDCLKB_MASK (0xCF)
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#define GPIO_MSCR_SDR_SDCLK_MASK (0xF3)
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#define GPIO_MSCR_SDR_SDRAM_MASK (0xFC)
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#define MSCR_25VDDR (0x03)
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#define MSCR_18VDDR_FULL (0x02)
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#define MSCR_OPENDRAIN (0x01)
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#define MSCR_18VDDR_HALF (0x00)
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#define GPIO_DSCR_I2C(x) ((x) & 0x03)
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#define GPIO_DSCR_I2C_MASK (0xFC)
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#define GPIO_DSCR_MISC_DBG(x) (((x) & 0x03) << 4)
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#define GPIO_DSCR_MISC_DBG_MASK (0xCF)
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#define GPIO_DSCR_MISC_RSTOUT(x) (((x) & 0x03) << 2)
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#define GPIO_DSCR_MISC_RSTOUT_MASK (0xF3)
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#define GPIO_DSCR_MISC_TIMER(x) ((x) & 0x03)
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#define GPIO_DSCR_MISC_TIMER_MASK (0xFC)
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#define GPIO_DSCR_FEC(x) ((x) & 0x03)
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#define GPIO_DSCR_FEC_MASK (0xFC)
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#define GPIO_DSCR_UART_UART1(x) (((x) & 0x03) << 4)
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#define GPIO_DSCR_UART_UART1_MASK (0xCF)
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#define GPIO_DSCR_UART_UART0(x) (((x) & 0x03) << 2)
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#define GPIO_DSCR_UART_UART0_MASK (0xF3)
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#define GPIO_DSCR_UART_IRQ(x) ((x) & 0x03)
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#define GPIO_DSCR_UART_IRQ_MASK (0xFC)
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#define GPIO_DSCR_QSPI(x) ((x) & 0x03)
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#define GPIO_DSCR_QSPI_MASK (0xFC)
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#define DSCR_50PF (0x03)
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#define DSCR_30PF (0x02)
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#define DSCR_20PF (0x01)
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#define DSCR_10PF (0x00)
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/* *** Phase Locked Loop (PLL) *** */
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#define PLL_PODR_CPUDIV(x) (((x) & 0x0F) << 4)
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#define PLL_PODR_CPUDIV_MASK (0x0F)
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#define PLL_PODR_BUSDIV(x) ((x) & 0x0F)
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#define PLL_PODR_BUSDIV_MASK (0xF0)
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#define PLL_PCR_DITHEN (0x80)
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#define PLL_PCR_DITHDEV(x) ((x) & 0x07)
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#define PLL_PCR_DITHDEV_MASK (0xF8)
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#endif /* __M520X__ */
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