u-boot/arch
Andy Fleming 3e4c3137d6 e6500: Move L1 enablement after L2 enablement
The L1 D-cache on e6500 is write-through. This means that it's not
considered a good idea to have the L1 up and running if the L2 is
disabled. We don't actually *use* the L1 until after the L2 is
brought up on e6500, so go ahead and move the L1 enablement after
that code is done.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:25 -05:00
..
arm lib: consolidate hang() 2013-05-01 16:41:08 -04:00
avr32 avr32: fix relocation address calculation 2013-05-13 10:35:12 +02:00
blackfin lib: consolidate hang() 2013-05-01 16:41:08 -04:00
m68k lib: consolidate hang() 2013-05-01 16:41:08 -04:00
microblaze gpio: Add support for microblaze xilinx GPIO 2013-05-09 11:20:08 +02:00
mips lib: consolidate hang() 2013-05-01 16:41:08 -04:00
nds32 nds32: Use sections header to obtain link symbols 2013-05-08 12:38:10 +08:00
nios2 lib: consolidate hang() 2013-05-01 16:41:08 -04:00
openrisc openrisc: move board linker script(s) to a common in cpu/ 2013-05-10 08:16:33 -04:00
powerpc e6500: Move L1 enablement after L2 enablement 2013-05-14 16:00:25 -05:00
sandbox sandbox: Allow -c argument to provide a command list 2013-05-01 11:17:21 -04:00
sh lib: consolidate hang() 2013-05-01 16:41:08 -04:00
sparc lib: consolidate hang() 2013-05-01 16:41:08 -04:00
x86 x86: Add coreboot timestamps 2013-05-13 13:33:22 -07:00
.gitignore update include/asm/ gitignore after move 2010-05-07 00:17:30 +02:00