Paul Gortmaker 3e3262bd14 sbc8548: enable support for hardware SPD errata workaround ... Existing boards by default have an issue where the LBC SDRAM SPD EEPROM and the DDR2 SDRAM SPD EEPROM both land at 0x51. After the hardware modification listed in the README is made, then the DDR2 SPD EEPROM appears at 0x53. So this implements a board specific get_spd() by taking advantage of the existing weak linkage, that 1st tries reading at 0x53 and then if that fails, it falls back to the old 0x51. Since the old dependency issue of "SPD implies no LBC SDRAM" gets removed with the hardware errata fix, remove that restriction in the code, so both LBC SDRAM and SPD can be selected. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>		2012-01-11 13:59:14 -06:00
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ddr.c	sbc8548: enable support for hardware SPD errata workaround	2012-01-11 13:59:14 -06:00
law.c	sbc8548: Make enabling SPD RAM configuration work	2012-01-11 13:59:07 -06:00
Makefile	punt unused clean/distclean targets	2011-10-15 22:20:36 +02:00
sbc8548.c	sbc8548: relocate fixed ddr init code to ddr.c file	2012-01-11 13:59:12 -06:00
tlb.c	sbc8548: Make enabling SPD RAM configuration work	2012-01-11 13:59:07 -06:00