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https://github.com/AsahiLinux/u-boot
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c2ccc9e5cb
Add Cadence PCIe endpoint driver supporting configuration of header, bars and MSI for device. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
177 lines
4.8 KiB
C
177 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019
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* Written by Ramon Fried <ramon.fried@gmail.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <pci_ep.h>
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#include <linux/sizes.h>
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#include <linux/log2.h>
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#include "pcie-cadence.h"
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DECLARE_GLOBAL_DATA_PTR;
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static int cdns_write_header(struct udevice *dev, uint fn,
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struct pci_ep_header *hdr)
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{
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struct cdns_pcie *pcie = dev_get_priv(dev);
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cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
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cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
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cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG,
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hdr->progif_code);
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cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
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hdr->subclass_code |
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hdr->baseclass_code << 8);
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cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
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hdr->cache_line_size);
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cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID,
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hdr->subsys_id);
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cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN,
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hdr->interrupt_pin);
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/*
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* Vendor ID can only be modified from function 0, all other functions
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* use the same vendor ID as function 0.
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*/
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if (fn == 0) {
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/* Update the vendor IDs. */
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u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
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CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
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cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
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}
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return 0;
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}
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static int cdns_set_bar(struct udevice *dev, uint fn, struct pci_bar *ep_bar)
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{
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struct cdns_pcie *pcie = dev_get_priv(dev);
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dma_addr_t bar_phys = ep_bar->phys_addr;
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enum pci_barno bar = ep_bar->barno;
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int flags = ep_bar->flags;
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u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
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u64 sz;
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/* BAR size is 2^(aperture + 7) */
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sz = max_t(size_t, ep_bar->size, CDNS_PCIE_EP_MIN_APERTURE);
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/*
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* roundup_pow_of_two() returns an unsigned long, which is not suited
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* for 64bit values.
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*/
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sz = 1ULL << fls64(sz - 1);
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aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
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if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
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ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
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} else {
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bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
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bool is_64bits = (sz > SZ_2G) |
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!!(ep_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64);
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if (is_64bits && (bar & 1))
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return -EINVAL;
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if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
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ep_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
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if (is_64bits && is_prefetch)
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ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
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else if (is_prefetch)
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ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
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else if (is_64bits)
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ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
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else
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ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
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}
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addr0 = lower_32_bits(bar_phys);
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addr1 = upper_32_bits(bar_phys);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
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addr0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
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addr1);
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if (bar < BAR_4) {
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reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
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b = bar;
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} else {
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reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
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b = bar - BAR_4;
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}
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cfg = cdns_pcie_readl(pcie, reg);
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cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
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CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
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cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
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CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
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cdns_pcie_writel(pcie, reg, cfg);
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return 0;
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}
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static int cdns_set_msi(struct udevice *dev, uint fn, uint mmc)
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{
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struct cdns_pcie *pcie = dev_get_priv(dev);
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u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
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/*
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* Set the Multiple Message Capable bitfield into the Message Control
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* register.
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*/
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u16 flags;
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flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
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flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1);
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flags |= PCI_MSI_FLAGS_64BIT;
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flags &= ~PCI_MSI_FLAGS_MASKBIT;
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cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags);
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return 0;
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}
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static struct pci_ep_ops cdns_pci_ep_ops = {
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.write_header = cdns_write_header,
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.set_bar = cdns_set_bar,
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.set_msi = cdns_set_msi,
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};
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static int cdns_pci_ep_probe(struct udevice *dev)
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{
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struct cdns_pcie *pdata = dev_get_priv(dev);
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pdata->reg_base = (void __iomem *)devfdt_get_addr(dev);
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if (!pdata->reg_base)
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return -ENOMEM;
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pdata->max_functions = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"max-functions", 1);
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pdata->max_regions = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"cdns,max-outbound-regions", 8);
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return 0;
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}
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static int cdns_pci_ep_remove(struct udevice *dev)
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{
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return 0;
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}
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const struct udevice_id cadence_pci_ep_of_match[] = {
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{ .compatible = "cdns,cdns-pcie-ep" },
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{ }
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};
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U_BOOT_DRIVER(cdns_pcie) = {
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.name = "cdns,pcie-ep",
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.id = UCLASS_PCI_EP,
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.of_match = cadence_pci_ep_of_match,
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.ops = &cdns_pci_ep_ops,
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.probe = cdns_pci_ep_probe,
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.remove = cdns_pci_ep_remove,
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.priv_auto_alloc_size = sizeof(struct cdns_pcie),
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};
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