mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
219 lines
6.6 KiB
C
219 lines
6.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* MCF5329 Internal Memory Map
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*/
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#ifndef __IMMAP_5235__
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#define __IMMAP_5235__
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#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
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#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
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#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
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#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
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#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
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#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
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#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
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#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
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#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
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#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
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#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300)
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#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340)
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#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400)
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#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440)
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#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480)
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#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0)
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#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00)
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#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00)
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#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00)
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#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000)
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#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400)
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#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000)
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#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000)
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#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000)
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#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000)
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#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000)
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#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000)
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#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000)
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#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000)
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#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000)
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#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000)
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#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000)
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#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000)
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#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000)
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#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000)
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#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000)
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#include <asm/coldfire/eport.h>
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#include <asm/coldfire/flexbus.h>
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#include <asm/coldfire/flexcan.h>
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#include <asm/coldfire/intctrl.h>
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#include <asm/coldfire/mdha.h>
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#include <asm/coldfire/qspi.h>
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#include <asm/coldfire/rng.h>
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#include <asm/coldfire/skha.h>
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/* System Control Module register */
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typedef struct scm_ctrl {
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u32 ipsbar; /* 0x00 - MBAR */
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u32 res1; /* 0x04 */
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u32 rambar; /* 0x08 - RAMBAR */
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u32 res2; /* 0x0C */
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u8 crsr; /* 0x10 Core Reset Status Register */
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u8 cwcr; /* 0x11 Core Watchdog Control Register */
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u8 lpicr; /* 0x12 Low-Power Interrupt Control Register */
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u8 cwsr; /* 0x13 Core Watchdog Service Register */
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u32 dmareqc; /* 0x14 */
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u32 res3; /* 0x18 */
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u32 mpark; /* 0x1C */
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u8 mpr; /* 0x20 */
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u8 res4[3]; /* 0x21 - 0x23 */
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u8 pacr0; /* 0x24 */
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u8 pacr1; /* 0x25 */
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u8 pacr2; /* 0x26 */
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u8 pacr3; /* 0x27 */
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u8 pacr4; /* 0x28 */
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u32 res5; /* 0x29 */
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u8 pacr5; /* 0x2a */
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u8 pacr6; /* 0x2b */
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u8 pacr7; /* 0x2c */
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u32 res6; /* 0x2d */
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u8 pacr8; /* 0x2e */
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u32 res7; /* 0x2f */
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u8 gpacr; /* 0x30 */
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u8 res8[3]; /* 0x31 - 0x33 */
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} scm_t;
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/* SDRAM controller registers */
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typedef struct sdram_ctrl {
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u16 dcr; /* 0x00 Control register */
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u16 res1[3]; /* 0x02 - 0x07 */
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u32 dacr0; /* 0x08 address and control register 0 */
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u32 dmr0; /* 0x0C mask register block 0 */
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u32 dacr1; /* 0x10 address and control register 1 */
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u32 dmr1; /* 0x14 mask register block 1 */
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} sdram_t;
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typedef struct canex_ctrl {
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can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
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} canex_t;
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/* GPIO port registers */
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typedef struct gpio_ctrl {
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/* Port Output Data Registers */
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u8 podr_addr; /* 0x00 */
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u8 podr_datah; /* 0x01 */
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u8 podr_datal; /* 0x02 */
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u8 podr_busctl; /* 0x03 */
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u8 podr_bs; /* 0x04 */
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u8 podr_cs; /* 0x05 */
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u8 podr_sdram; /* 0x06 */
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u8 podr_feci2c; /* 0x07 */
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u8 podr_uarth; /* 0x08 */
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u8 podr_uartl; /* 0x09 */
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u8 podr_qspi; /* 0x0A */
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u8 podr_timer; /* 0x0B */
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u8 podr_etpu; /* 0x0C */
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u8 res1[3]; /* 0x0D - 0x0F */
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/* Port Data Direction Registers */
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u8 pddr_addr; /* 0x10 */
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u8 pddr_datah; /* 0x11 */
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u8 pddr_datal; /* 0x12 */
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u8 pddr_busctl; /* 0x13 */
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u8 pddr_bs; /* 0x14 */
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u8 pddr_cs; /* 0x15 */
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u8 pddr_sdram; /* 0x16 */
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u8 pddr_feci2c; /* 0x17 */
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u8 pddr_uarth; /* 0x18 */
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u8 pddr_uartl; /* 0x19 */
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u8 pddr_qspi; /* 0x1A */
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u8 pddr_timer; /* 0x1B */
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u8 pddr_etpu; /* 0x1C */
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u8 res2[3]; /* 0x1D - 0x1F */
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/* Port Data Direction Registers */
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u8 ppdsdr_addr; /* 0x20 */
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u8 ppdsdr_datah; /* 0x21 */
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u8 ppdsdr_datal; /* 0x22 */
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u8 ppdsdr_busctl; /* 0x23 */
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u8 ppdsdr_bs; /* 0x24 */
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u8 ppdsdr_cs; /* 0x25 */
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u8 ppdsdr_sdram; /* 0x26 */
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u8 ppdsdr_feci2c; /* 0x27 */
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u8 ppdsdr_uarth; /* 0x28 */
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u8 ppdsdr_uartl; /* 0x29 */
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u8 ppdsdr_qspi; /* 0x2A */
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u8 ppdsdr_timer; /* 0x2B */
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u8 ppdsdr_etpu; /* 0x2C */
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u8 res3[3]; /* 0x2D - 0x2F */
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/* Port Clear Output Data Registers */
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u8 pclrr_addr; /* 0x30 */
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u8 pclrr_datah; /* 0x31 */
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u8 pclrr_datal; /* 0x32 */
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u8 pclrr_busctl; /* 0x33 */
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u8 pclrr_bs; /* 0x34 */
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u8 pclrr_cs; /* 0x35 */
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u8 pclrr_sdram; /* 0x36 */
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u8 pclrr_feci2c; /* 0x37 */
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u8 pclrr_uarth; /* 0x38 */
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u8 pclrr_uartl; /* 0x39 */
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u8 pclrr_qspi; /* 0x3A */
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u8 pclrr_timer; /* 0x3B */
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u8 pclrr_etpu; /* 0x3C */
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u8 res4[3]; /* 0x3D - 0x3F */
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/* Pin Assignment Registers */
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u8 par_ad; /* 0x40 */
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u8 res5; /* 0x41 */
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u16 par_busctl; /* 0x42 */
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u8 par_bs; /* 0x44 */
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u8 par_cs; /* 0x45 */
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u8 par_sdram; /* 0x46 */
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u8 par_feci2c; /* 0x47 */
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u16 par_uart; /* 0x48 */
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u8 par_qspi; /* 0x4A */
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u8 res6; /* 0x4B */
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u16 par_timer; /* 0x4C */
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u8 par_etpu; /* 0x4E */
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u8 res7; /* 0x4F */
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/* Drive Strength Control Registers */
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u8 dscr_eim; /* 0x50 */
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u8 dscr_etpu; /* 0x51 */
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u8 dscr_feci2c; /* 0x52 */
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u8 dscr_uart; /* 0x53 */
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u8 dscr_qspi; /* 0x54 */
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u8 dscr_timer; /* 0x55 */
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u16 res8; /* 0x56 */
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} gpio_t;
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/*Chip configuration module registers */
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typedef struct ccm_ctrl {
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u8 rcr; /* 0x01 */
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u8 rsr; /* 0x02 */
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u16 res1; /* 0x03 */
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u16 ccr; /* 0x04 Chip configuration register */
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u16 lpcr; /* 0x06 Low-power Control register */
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u16 rcon; /* 0x08 Rreset configuration register */
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u16 cir; /* 0x0a Chip identification register */
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} ccm_t;
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/* Clock Module registers */
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typedef struct pll_ctrl {
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u32 syncr; /* 0x00 synthesizer control register */
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u32 synsr; /* 0x04 synthesizer status register */
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} pll_t;
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/* Watchdog registers */
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typedef struct wdog_ctrl {
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u16 cr; /* 0x00 Control register */
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u16 mr; /* 0x02 Modulus register */
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u16 cntr; /* 0x04 Count register */
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u16 sr; /* 0x06 Service register */
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} wdog_t;
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#endif /* __IMMAP_5235__ */
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