Manoj Sai 3da15f0b49 phy: rockchip-inno-usb2: Add USB2 PHY for rk3568 ... RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the OTG port of PHY0 support OTG mode with charging detection function, they are similar to previous Rockchip SoCs. However, there are three different designs for RK3568 USB 2.0 PHY. 1. RK3568 uses independent USB GRF module for each USB 2.0 PHY. 2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB. 3. The two ports of USB 2.0 PHY share one interrupt. This patch only PHY1 with necessary attributes required to function USBPHY1 on U-Boot. Co-developed-by: Ren Jianing <jianing.ren@rock-chips.com> Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com> Co-developed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>		2023-02-28 18:07:27 +08:00
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Kconfig	pci: Add Rockchip dwc based PCIe controller driver	2021-01-21 12:00:45 +08:00
Makefile	phy: rockchip: Add Rockchip Synopsys PCIe 3.0 PHY	2021-01-21 12:00:45 +08:00
phy-rockchip-inno-usb2.c	phy: rockchip-inno-usb2: Add USB2 PHY for rk3568	2023-02-28 18:07:27 +08:00
phy-rockchip-pcie.c	common: Drop asm/global_data.h from common header	2021-02-02 15:33:42 -05:00
phy-rockchip-snps-pcie3.c	phy: rockchip: Add Rockchip Synopsys PCIe 3.0 PHY	2021-01-21 12:00:45 +08:00
phy-rockchip-typec.c	common: Drop asm/global_data.h from common header	2021-02-02 15:33:42 -05:00