mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-29 08:01:08 +00:00
45651a3d69
Trying to boot a fitImage after a successful hab_auth_img operation
causes the following error:
## Loading kernel from FIT Image at 88000000 ...
Using 'conf-imx7d-smegw01.dtb' configuration
Trying 'kernel-1' kernel subimage
Description: Linux kernel
Type: Kernel Image
Compression: uncompressed
Data Start: 0x8800010c
Data Size: 9901752 Bytes = 9.4 MiB
Architecture: ARM
OS: Linux
Load Address: 0x80800000
Entry Point: 0x80800000
Hash algo: sha256
Hash value: 28f8779bbf010780f16dd3d84ecb9b604c44c5c2cf7acd098c264a2d3f68e969
Verifying Hash Integrity ... sha256Error in SEC deq
CAAM was not setup properly or it is faulty error!
The reason for this error is that the BootROM uses the CAAM Job Ring 0,
so disable its node in U-Boot to avoid the resource conflict.
imx8m dtsi files also have the Job Ring 0 disable since the following
kernel commit:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/arch?h=v6.5&id=dc9c1ceb555ff661e6fc1081434600771f29657c
For a temporary solution, disable the Job Ring 0 in imx7s-u-boot.dtsi.
Reported-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
60 lines
1.5 KiB
Text
60 lines
1.5 KiB
Text
#include "imx7s-u-boot.dtsi"
|
|
|
|
&fec2 {
|
|
status = "disable";
|
|
};
|
|
|
|
&usbotg1 {
|
|
dr_mode = "peripheral";
|
|
};
|
|
|
|
&usdhc1 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
|
|
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
|
|
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
|
|
};
|
|
|
|
&pinctrl_usdhc1 {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
|
|
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
|
|
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
|
|
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
|
|
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
|
|
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
|
|
>;
|
|
};
|
|
|
|
&iomuxc {
|
|
pinctrl_usdhc1_gpio: usdhc1gpiogrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
|
|
MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
|
|
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
|
|
MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_100mhz: usdhc1100mhzgrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
|
|
MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
|
|
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
|
|
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
|
|
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
|
|
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_200mhz: usdhc1200mhzgrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
|
|
MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
|
|
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
|
|
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
|
|
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
|
|
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
|
|
>;
|
|
};
|
|
};
|