mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 18:28:55 +00:00
371 lines
8.5 KiB
ArmAsm
371 lines
8.5 KiB
ArmAsm
/*
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* Most of this taken from Redboot hal_platform_setup.h with cleanup
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*
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* NOTE: I haven't clean this up considerably, just enough to get it
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* running. See hal_platform_setup.h for the source. See
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* board/cradle/lowlevel_init.S for another PXA250 setup that is
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* much cleaner.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/pxa-regs.h>
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DRAM_SIZE: .long CFG_DRAM_SIZE
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/* wait for coprocessor write complete */
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.macro CPWAIT reg
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mrc p15,0,\reg,c2,c0,0
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mov \reg,\reg
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sub pc,pc,#4
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.endm
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.macro wait time
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ldr r2, =OSCR
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mov r3, #0
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str r3, [r2]
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0:
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ldr r3, [r2]
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cmp r3, \time
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bls 0b
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.endm
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/*
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* Memory setup
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*/
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.globl lowlevel_init
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lowlevel_init:
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/* Set up GPIO pins first ----------------------------------------- */
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mov r10, lr
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/* Configure GPIO Pins 41 - 48 as UART1 / altern. Fkt. 2 */
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ldr r0, =0x40E10438 @ GPIO41 FFRXD
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ldr r1, =0x802
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str r1, [r0]
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ldr r0, =0x40E1043C @ GPIO42 FFTXD
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ldr r1, =0x802
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str r1, [r0]
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ldr r0, =0x40E10440 @ GPIO43 FFCTS
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ldr r1, =0x802
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str r1, [r0]
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ldr r0, =0x40E10444 @ GPIO 44 FFDCD
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ldr r1, =0x802
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str r1, [r0]
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ldr r0, =0x40E10448 @ GPIO 45 FFDSR
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ldr r1, =0x802
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str r1, [r0]
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ldr r0, =0x40E1044C @ GPIO 46 FFRI
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ldr r1, =0x802
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str r1, [r0]
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ldr r0, =0x40E10450 @ GPIO 47 FFDTR
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ldr r1, =0x802
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str r1, [r0]
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ldr r0, =0x40E10454 @ GPIO 48
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ldr r1, =0x802
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str r1, [r0]
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/* tebrandt - ASCR, clear the RDH bit */
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ldr r0, =ASCR
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ldr r1, [r0]
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bic r1, r1, #0x80000000
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str r1, [r0]
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/* ---------------------------------------------------------------- */
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/* Enable memory interface */
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/* */
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/* The sequence below is based on the recommended init steps */
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/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
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/* Chapter 10. */
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/* ---------------------------------------------------------------- */
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/* ---------------------------------------------------------------- */
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/* Step 1: Wait for at least 200 microsedonds to allow internal */
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/* clocks to settle. Only necessary after hard reset... */
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/* FIXME: can be optimized later */
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/* ---------------------------------------------------------------- */
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/* mk: replaced with wait macro */
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/* ldr r3, =OSCR /\* reset the OS Timer Count to zero *\/ */
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/* mov r2, #0 */
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/* str r2, [r3] */
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/* ldr r4, =0x300 /\* really 0x2E1 is about 200usec, *\/ */
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/* /\* so 0x300 should be plenty *\/ */
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/* 1: */
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/* ldr r2, [r3] */
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/* cmp r4, r2 */
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/* bgt 1b */
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wait #300
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mem_init:
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/* configure the MEMCLKCFG register */
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ldr r1, =MEMCLKCFG
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ldr r2, =0x00010001
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str r2, [r1] @ WRITE
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
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/* set CSADRCFG[0] to data flash SRAM mode */
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ldr r1, =CSADRCFG0
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ldr r2, =0x00320809
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str r2, [r1] @ WRITE
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
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/* set CSADRCFG[1] to data flash SRAM mode */
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ldr r1, =CSADRCFG1
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ldr r2, =0x00320809
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str r2, [r1] @ WRITE
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
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/* set MSC 0 register for SRAM memory */
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ldr r1, =MSC0
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ldr r2, =0x11191119
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str r2, [r1] @ WRITE
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
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/* set CSADRCFG[2] to data flash SRAM mode */
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ldr r1, =CSADRCFG2
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ldr r2, =0x00320809
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str r2, [r1] @ WRITE
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
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/* set CSADRCFG[3] to VLIO mode */
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ldr r1, =CSADRCFG3
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ldr r2, =0x0032080B
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str r2, [r1] @ WRITE
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
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/* set MSC 1 register for VLIO memory */
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ldr r1, =MSC1
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ldr r2, =0x123C1119
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str r2, [r1] @ WRITE
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
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#if 0
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/* This does not work in Zylonite. -SC */
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ldr r0, =0x15fffff0
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ldr r1, =0xb10b
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str r1, [r0]
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str r1, [r0, #4]
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#endif
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/* Configure ACCR Register */
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ldr r0, =ACCR @ ACCR
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ldr r1, =0x0180b108
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str r1, [r0]
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ldr r1, [r0]
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/* Configure MDCNFG Register */
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ldr r0, =MDCNFG @ MDCNFG
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ldr r1, =0x403
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str r1, [r0]
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ldr r1, [r0]
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/* Perform Resistive Compensation by configuring RCOMP register */
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ldr r1, =RCOMP @ RCOMP
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ldr r2, =0x000000ff
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str r2, [r1]
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ldr r2, [r1]
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/* Configure MDMRS Register for SDCS0 */
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ldr r1, =MDMRS @ MDMRS
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ldr r2, =0x60000023
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ldr r3, [r1]
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orr r2, r2, r3
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str r2, [r1]
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ldr r2, [r1]
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/* Configure MDMRS Register for SDCS1 */
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ldr r1, =MDMRS @ MDMRS
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ldr r2, =0xa0000023
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ldr r3, [r1]
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orr r2, r2, r3
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str r2, [r1]
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ldr r2, [r1]
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/* Configure MDREFR */
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ldr r1, =MDREFR @ MDREFR
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ldr r2, =0x00000006
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str r2, [r1]
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ldr r2, [r1]
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/* Configure EMPI */
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ldr r1, =EMPI @ EMPI
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ldr r2, =0x80000000
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str r2, [r1]
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ldr r2, [r1]
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/* Hardware DDR Read-Strobe Delay Calibration */
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ldr r0, =DDR_HCAL @ DDR_HCAL
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ldr r1, =0x803ffc07 @ the offset is correct? -SC
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str r1, [r0]
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wait #5
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ldr r1, [r0]
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/* Here we assume the hardware calibration alwasy be successful. -SC */
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/* Set DMCEN bit in MDCNFG Register */
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ldr r0, =MDCNFG @ MDCNFG
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ldr r1, [r0]
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orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
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str r1, [r0]
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/* scrub/init SDRAM if enabled/present */
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/* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */
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/* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */
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/* mov r8,r12 /\* save DRAM size (mk: why???) *\/ */
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ldr r8, =0xa0000000 /* base address of SDRAM (CFG_DRAM_BASE) */
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ldr r9, =0x04000000 /* size of memory to scrub (CFG_DRAM_SIZE) */
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mov r0, #0 /* scrub with 0x0000:0000 */
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mov r1, #0
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mov r2, #0
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mov r3, #0
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mov r4, #0
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mov r5, #0
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mov r6, #0
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mov r7, #0
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10: /* fastScrubLoop */
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subs r9, r9, #32 /* 32 bytes/line */
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stmia r8!, {r0-r7}
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beq 15f
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b 10b
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15:
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/* Mask all interrupts */
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mov r1, #0
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mcr p6, 0, r1, c1, c0, 0 @ ICMR
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/* Disable software and data breakpoints */
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mov r0, #0
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mcr p15,0,r0,c14,c8,0 /* ibcr0 */
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mcr p15,0,r0,c14,c9,0 /* ibcr1 */
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mcr p15,0,r0,c14,c4,0 /* dbcon */
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/* Enable all debug functionality */
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mov r0,#0x80000000
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mcr p14,0,r0,c10,c0,0 /* dcsr */
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/* We are finished with Intel's memory controller initialisation */
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/* ---------------------------------------------------------------- */
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/* End lowlevel_init */
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/* ---------------------------------------------------------------- */
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endlowlevel_init:
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mov pc, lr
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/*
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@********************************************************************************
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@ DDR calibration
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@
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@ This function is used to calibrate DQS delay lines.
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@ Monahans supports three ways to do it. One is software
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@ calibration. Two is hardware calibration. Three is hybrid
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@ calibration.
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@
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@ TBD
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@ -SC
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ddr_calibration:
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@ Case 1: Write the correct delay value once
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@ Configure DDR_SCAL Register
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ldr r0, =DDR_SCAL @ DDR_SCAL
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q ldr r1, =0xaf2f2f2f
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str r1, [r0]
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ldr r1, [r0]
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*/
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/* @ Case 2: Software Calibration
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@ Write test pattern to memory
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ldr r5, =0x0faf0faf @ Data Pattern
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ldr r4, =0xa0000000 @ DDR ram
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str r5, [r4]
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mov r1, =0x0 @ delay count
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mov r6, =0x0
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mov r7, =0x0
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ddr_loop1:
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add r1, r1, =0x1
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cmp r1, =0xf
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ble end_loop
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mov r3, r1
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mov r0, r1, lsl #30
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orr r3, r3, r0
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mov r0, r1, lsl #22
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orr r3, r3, r0
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mov r0, r1, lsl #14
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orr r3, r3, r0
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orr r3, r3, =0x80000000
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ldr r2, =DDR_SCAL
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str r3, [r2]
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ldr r2, [r4]
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cmp r2, r5
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bne ddr_loop1
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mov r6, r1
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ddr_loop2:
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add r1, r1, =0x1
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cmp r1, =0xf
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ble end_loop
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mov r3, r1
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mov r0, r1, lsl #30
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orr r3, r3, r0
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mov r0, r1, lsl #22
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orr r3, r3, r0
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mov r0, r1, lsl #14
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orr r3, r3, r0
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orr r3, r3, =0x80000000
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ldr r2, =DDR_SCAL
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str r3, [r2]
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ldr r2, [r4]
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cmp r2, r5
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be ddr_loop2
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mov r7, r2
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add r3, r6, r7
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lsr r3, r3, =0x1
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mov r0, r1, lsl #30
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orr r3, r3, r0
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mov r0, r1, lsl #22
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orr r3, r3, r0
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mov r0, r1, lsl #14
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orr r3, r3, r0
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orr r3, r3, =0x80000000
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ldr r2, =DDR_SCAL
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end_loop:
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@ Case 3: Hardware Calibratoin
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ldr r0, =DDR_HCAL @ DDR_HCAL
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ldr r1, =0x803ffc07 @ the offset is correct? -SC
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str r1, [r0]
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wait #5
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ldr r1, [r0]
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mov pc, lr
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*/
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