mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 05:42:58 +00:00
d3daba10f1
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
80 lines
2.1 KiB
C
80 lines
2.1 KiB
C
/*
|
|
* hardware_am43xx.h
|
|
*
|
|
* AM43xx hardware specific header
|
|
*
|
|
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#ifndef __AM43XX_HARDWARE_AM43XX_H
|
|
#define __AM43XX_HARDWARE_AM43XX_H
|
|
|
|
/* Module base addresses */
|
|
|
|
/* UART Base Address */
|
|
#define UART0_BASE 0x44E09000
|
|
|
|
/* GPIO Base address */
|
|
#define GPIO2_BASE 0x481AC000
|
|
|
|
/* Watchdog Timer */
|
|
#define WDT_BASE 0x44E35000
|
|
|
|
/* Control Module Base Address */
|
|
#define CTRL_BASE 0x44E10000
|
|
#define CTRL_DEVICE_BASE 0x44E10600
|
|
|
|
/* PRCM Base Address */
|
|
#define PRCM_BASE 0x44DF0000
|
|
#define CM_WKUP 0x44DF2800
|
|
#define CM_PER 0x44DF8800
|
|
#define CM_DPLL 0x44DF4200
|
|
#define CM_RTC 0x44DF8500
|
|
|
|
#define PRM_RSTCTRL (PRCM_BASE + 0x4000)
|
|
#define PRM_RSTST (PRM_RSTCTRL + 4)
|
|
|
|
/* VTP Base address */
|
|
#define VTP0_CTRL_ADDR 0x44E10E0C
|
|
#define VTP1_CTRL_ADDR 0x48140E10
|
|
|
|
/* DDR Base address */
|
|
#define DDR_PHY_CMD_ADDR 0x44E12000
|
|
#define DDR_PHY_DATA_ADDR 0x44E120C8
|
|
#define DDR_PHY_CMD_ADDR2 0x47C0C800
|
|
#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
|
|
#define DDR_DATA_REGS_NR 2
|
|
|
|
/* CPSW Config space */
|
|
#define CPSW_MDIO_BASE 0x4A101000
|
|
|
|
/* RTC base address */
|
|
#define RTC_BASE 0x44E3E000
|
|
|
|
/* USB Clock Control */
|
|
#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
|
|
#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
|
|
#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1)
|
|
#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
|
|
|
|
#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
|
|
#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
|
|
#define USBPHYOCPSCP_MODULE_EN (1 << 1)
|
|
#define CM_DEVICE_INST 0x44df4100
|
|
|
|
/* Control status register */
|
|
#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31)
|
|
#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31
|
|
#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29)
|
|
#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29
|
|
#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22)
|
|
#define CTRL_SYSBOOT_15_14_SHIFT 22
|
|
|
|
#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0
|
|
#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1
|
|
|
|
#define NUM_CRYSTAL_FREQ 0x4
|
|
|
|
#endif /* __AM43XX_HARDWARE_AM43XX_H */
|