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AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for NOR to work on Rev.3 EVM. When GP0[11] is low, the SD0 interface will not work, but NOR flash will. Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> |
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davinci_misc.h | ||
emac_defs.h | ||
emif_defs.h | ||
gpio.h | ||
hardware.h | ||
i2c_defs.h | ||
nand_defs.h | ||
sdmmc_defs.h |