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u-boot/board/altera/arria5-socdk
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Marek Vasut 29aa439759 arm: socfpga: Fix ArriaV SoCDK PLL config 
Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot
"rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into
mainline to get a booting ArriaV SoCDK.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:21 +02:00
..
qts arm: socfpga: Fix ArriaV SoCDK PLL config 2015-08-23 11:56:21 +02:00
MAINTAINERS arm: socfpga: Fix MAINTAINERS entry for CV/AV SoCDK 2015-08-23 11:56:20 +02:00
Makefile arm: socfpga: Split Altera socfpga into AV and CV SoCDK 2015-08-23 11:56:19 +02:00
socfpga.c arm: socfpga: Split Altera socfpga into AV and CV SoCDK 2015-08-23 11:56:19 +02:00