mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 17:58:23 +00:00
7205e4075d
add FAT support for IDE, SCSI and USB
* Patches by Gleb Natapov, 2 Sep 2003:
- cleanup of POST code for unsupported architectures
- MPC824x locks way0 of data cache for use as initial RAM;
this patch unlocks it after relocation to RAM and invalidates
the locked entries.
* Patch by Gleb Natapov, 30 Aug 2003:
new I2C driver for mpc107 bridge. Now works from flash.
* Patch by Dave Ellis, 11 Aug 2003:
- JFFS2: fix typo in common/cmd_jffs2.c
- JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option
- JFFS2: remove node version 0 warning
- JFFS2: accept JFFS2 PADDING nodes
- SXNI855T: add AM29LV800 support
- SXNI855T: move environment from EEPROM to flash
- SXNI855T: boot from JFFS2 in NOR or NAND flash
* Patch by Bill Hargen, 11 Aug 2003:
fixes for I2C on MPC8240
- fix i2c_write routine
- fix iprobe command
- eliminates use of global variables, plus dead code, cleanup.
165 lines
5 KiB
C
165 lines
5 KiB
C
/*
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* (C) Copyright 2001
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* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _PIIX4_PCI_H
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#define _PIIX4_PCI_H
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/***************************************************************************
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* Defines PIIX4 Config Registers
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****************************************************************************/
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/* Function 0 ISA Bridge */
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#define PCI_CFG_PIIX4_IORT 0x4C /* 8 bit ISA Recovery Timer Reg (default 0x4D) */
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#define PCI_CFG_PIIX4_XBCS 0x4E /* 16 bit XBus Chip select reg (default 0x0003) */
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#define PCI_CFG_PIIX4_PIRQC 0x60 /* PCI IRQ Route Register 4 x 8bit (default )*/
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#define PCI_CFG_PIIX4_SERIRQ 0x64
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#define PCI_CFG_PIIX4_TOM 0x69
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#define PCI_CFG_PIIX4_MSTAT 0x6A
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#define PCI_CFG_PIIX4_MBDMA 0x76
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#define PCI_CFG_PIIX4_APICBS 0x80
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#define PCI_CFG_PIIX4_DLC 0x82
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#define PCI_CFG_PIIX4_PDMACFG 0x90
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#define PCI_CFG_PIIX4_DDMABS 0x92
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#define PCI_CFG_PIIX4_GENCFG 0xB0
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#define PCI_CFG_PIIX4_RTCCFG 0xCB
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/* IO Addresses */
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#define PIIX4_ISA_DMA1_CH0BA 0x00
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#define PIIX4_ISA_DMA1_CH0CA 0x01
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#define PIIX4_ISA_DMA1_CH1BA 0x02
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#define PIIX4_ISA_DMA1_CH1CA 0x03
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#define PIIX4_ISA_DMA1_CH2BA 0x04
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#define PIIX4_ISA_DMA1_CH2CA 0x05
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#define PIIX4_ISA_DMA1_CH3BA 0x06
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#define PIIX4_ISA_DMA1_CH3CA 0x07
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#define PIIX4_ISA_DMA1_CMDST 0x08
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#define PIIX4_ISA_DMA1_REQ 0x09
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#define PIIX4_ISA_DMA1_WSBM 0x0A
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#define PIIX4_ISA_DMA1_CH_MOD 0x0B
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#define PIIX4_ISA_DMA1_CLR_PT 0x0C
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#define PIIX4_ISA_DMA1_M_CLR 0x0D
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#define PIIX4_ISA_DMA1_CLR_M 0x0E
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#define PIIX4_ISA_DMA1_RWAMB 0x0F
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#define PIIX4_ISA_DMA2_CH0BA 0xC0
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#define PIIX4_ISA_DMA2_CH0CA 0xC1
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#define PIIX4_ISA_DMA2_CH1BA 0xC2
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#define PIIX4_ISA_DMA2_CH1CA 0xC3
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#define PIIX4_ISA_DMA2_CH2BA 0xC4
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#define PIIX4_ISA_DMA2_CH2CA 0xC5
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#define PIIX4_ISA_DMA2_CH3BA 0xC6
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#define PIIX4_ISA_DMA2_CH3CA 0xC7
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#define PIIX4_ISA_DMA2_CMDST 0xD0
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#define PIIX4_ISA_DMA2_REQ 0xD2
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#define PIIX4_ISA_DMA2_WSBM 0xD4
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#define PIIX4_ISA_DMA2_CH_MOD 0xD6
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#define PIIX4_ISA_DMA2_CLR_PT 0xD8
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#define PIIX4_ISA_DMA2_M_CLR 0xDA
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#define PIIX4_ISA_DMA2_CLR_M 0xDC
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#define PIIX4_ISA_DMA2_RWAMB 0xDE
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#define PIIX4_ISA_INT1_ICW1 0x20
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#define PIIX4_ISA_INT1_OCW2 0x20
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#define PIIX4_ISA_INT1_OCW3 0x20
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#define PIIX4_ISA_INT1_ICW2 0x21
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#define PIIX4_ISA_INT1_ICW3 0x21
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#define PIIX4_ISA_INT1_ICW4 0x21
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#define PIIX4_ISA_INT1_OCW1 0x21
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#define PIIX4_ISA_INT1_ELCR 0x4D0
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#define PIIX4_ISA_INT2_ICW1 0xA0
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#define PIIX4_ISA_INT2_OCW2 0xA0
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#define PIIX4_ISA_INT2_OCW3 0xA0
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#define PIIX4_ISA_INT2_ICW2 0xA1
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#define PIIX4_ISA_INT2_ICW3 0xA1
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#define PIIX4_ISA_INT2_ICW4 0xA1
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#define PIIX4_ISA_INT2_OCW1 0xA1
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#define PIIX4_ISA_INT2_IMR 0xA1 /* read only */
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#define PIIX4_ISA_INT2_ELCR 0x4D1
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#define PIIX4_ISA_TMR0_CNT_ST 0x40
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#define PIIX4_ISA_TMR1_CNT_ST 0x41
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#define PIIX4_ISA_TMR2_CNT_ST 0x42
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#define PIIX4_ISA_TMR_TCW 0x43
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#define PIIX4_ISA_RST_XBUS 0x60
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#define PIIX4_ISA_NMI_CNT_ST 0x61
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#define PIIX4_ISA_NMI_ENABLE 0x70
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#define PIIX4_ISA_RTC_INDEX 0x70
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#define PIIX4_ISA_RTC_DATA 0x71
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#define PIIX4_ISA_RTCEXT_IND 0x70
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#define PIIX4_ISA_RTCEXT_DATA 0x71
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#define PIIX4_ISA_DMA1_CH2LPG 0x81
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#define PIIX4_ISA_DMA1_CH3LPG 0x82
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#define PIIX4_ISA_DMA1_CH1LPG 0x83
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#define PIIX4_ISA_DMA1_CH0LPG 0x87
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#define PIIX4_ISA_DMA2_CH2LPG 0x89
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#define PIIX4_ISA_DMA2_CH3LPG 0x8A
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#define PIIX4_ISA_DMA2_CH1LPG 0x8B
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#define PIIX4_ISA_DMA2_LPGRFR 0x8F
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#define PIIX4_ISA_PORT_92 0x92
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#define PIIX4_ISA_APM_CONTRL 0xB2
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#define PIIX4_ISA_APM_STATUS 0xB3
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#define PIIX4_ISA_COCPU_ERROR 0xF0
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/* Function 1 IDE Controller */
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#define PCI_CFG_PIIX4_BMIBA 0x20
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#define PCI_CFG_PIIX4_IDETIM 0x40
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#define PCI_CFG_PIIX4_SIDETIM 0x44
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#define PCI_CFG_PIIX4_UDMACTL 0x48
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#define PCI_CFG_PIIX4_UDMATIM 0x4A
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/* Function 2 USB Controller */
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#define PCI_CFG_PIIX4_SBRNUM 0x60
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#define PCI_CFG_PIIX4_LEGSUP 0xC0
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/* Function 3 Power Management */
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#define PCI_CFG_PIIX4_PMBA 0x40
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#define PCI_CFG_PIIX4_CNTA 0x44
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#define PCI_CFG_PIIX4_CNTB 0x48
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#define PCI_CFG_PIIX4_GPICTL 0x4C
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#define PCI_CFG_PIIX4_DEVRESD 0x50
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#define PCI_CFG_PIIX4_DEVACTA 0x54
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#define PCI_CFG_PIIX4_DEVACTB 0x58
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#define PCI_CFG_PIIX4_DEVRESA 0x5C
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#define PCI_CFG_PIIX4_DEVRESB 0x60
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#define PCI_CFG_PIIX4_DEVRESC 0x64
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#define PCI_CFG_PIIX4_DEVRESE 0x68
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#define PCI_CFG_PIIX4_DEVRESF 0x6C
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#define PCI_CFG_PIIX4_DEVRESG 0x70
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#define PCI_CFG_PIIX4_DEVRESH 0x74
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#define PCI_CFG_PIIX4_DEVRESI 0x78
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#define PCI_CFG_PIIX4_PMMISC 0x80
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#define PCI_CFG_PIIX4_SMBBA 0x90
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#endif
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