mirror of
https://github.com/AsahiLinux/u-boot
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1d21e1b97c
Fix warnings reported by sparse: - ... was not declared. Should it be static?" - cast to restricted __be32 While fixing those, the type conflict of cci500_init() was found. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
491 lines
14 KiB
C
491 lines
14 KiB
C
/*
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* Copyright (C) 2016 Socionext Inc.
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*/
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#include <common.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <asm/processor.h>
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#include "../init.h"
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#include "ddrphy-regs.h"
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#include "umc64-regs.h"
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#define DDR_FREQ 1600
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#define DRAM_CH_NR 2
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#define RANK_BLOCKS_TR 2
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enum dram_freq {
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DRAM_FREQ_1600M,
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DRAM_FREQ_NR,
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};
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enum dram_size {
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DRAM_SZ_256M,
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DRAM_SZ_512M,
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DRAM_SZ_NR,
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};
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/* PHY */
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static const int rof_pos_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
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static const int rof_neg_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
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static const int rof_pos_shift[RANK_BLOCKS_TR][2] = { {-35, -35}, {-35, -35} };
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static const int rof_neg_shift[RANK_BLOCKS_TR][2] = { {-17, -17}, {-17, -17} };
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static const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} };
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/* Register address */
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#define PHY_ZQ0CR1 0x00000184
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#define PHY_ZQ1CR1 0x00000194
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#define PHY_ZQ2CR1 0x000001A4
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#define PHY_DX0GCR 0x000001C0
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#define PHY_DX0GTR 0x000001F0
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#define PHY_DX1GCR 0x00000200
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#define PHY_DX1GTR 0x00000230
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#define PHY_DX2GCR 0x00000240
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#define PHY_DX2GTR 0x00000270
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#define PHY_DX3GCR 0x00000280
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#define PHY_DX3GTR 0x000002B0
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#define PHY_DXMDLR(dx) (0x000001EC + 0x40 * (dx))
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#define PHY_DXLCDLR0(dx) (0x000001E0 + 0x40 * (dx))
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#define PHY_DXLCDLR1(dx) (0x000001E4 + 0x40 * (dx))
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#define PHY_DXLCDLR2(dx) (0x000001E8 + 0x40 * (dx))
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#define PHY_DXBDLR1(dx) (0x000001D0 + 0x40 * (dx))
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#define PHY_DXBDLR2(dx) (0x000001D4 + 0x40 * (dx))
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/* MASK */
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#define PHY_ACBD_MASK 0x00FC0000
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#define PHY_CK0BD_MASK 0x0000003F
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#define PHY_CK1BD_MASK 0x00000FC0
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#define PHY_IPRD_MASK 0x000000FF
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#define PHY_WLD_MASK(rank) (0xFF << (8 * (rank)))
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#define PHY_DQSGD_MASK(rank) (0xFF << (8 * (rank)))
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#define PHY_DQSGX_MASK BIT(6)
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#define PHY_DSWBD_MASK 0x3F000000 /* bit[29:24] */
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#define PHY_DSDQOE_MASK 0x00000FFF
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static void ddrphy_maskwritel(u32 data, u32 mask, void __iomem *addr)
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{
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u32 value;
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value = (readl(addr) & ~(mask)) | (data & mask);
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writel(value, addr);
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}
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static u32 ddrphy_maskreadl(u32 mask, void __iomem *addr)
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{
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return readl(addr) & mask;
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}
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/* step of 0.5T for PUB-byte */
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static u8 ddrphy_get_mdl(int dx, void __iomem *phy_base)
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{
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return ddrphy_maskreadl(PHY_IPRD_MASK, phy_base + PHY_DXMDLR(dx));
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}
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/* Calculating step for PUB-byte */
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static int ddrphy_hpstep(int delay, int dx, void __iomem *phy_base)
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{
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return delay * ddrphy_get_mdl(dx, phy_base) * DDR_FREQ / 1000000;
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}
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static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)
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{
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u32 tmp;
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tmp = readl(phy_base + PHY_PGCR1);
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if (enable)
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tmp &= ~PHY_PGCR1_INHVT;
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else
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tmp |= PHY_PGCR1_INHVT;
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writel(tmp, phy_base + PHY_PGCR1);
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if (!enable) {
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while (!(readl(phy_base + PHY_PGSR1) & PHY_PGSR1_VTSTOP))
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cpu_relax();
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}
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}
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static void ddrphy_set_ckoffset_qoffset(int delay_ckoffset0, int delay_ckoffset1,
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int delay_qoffset, int enable,
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void __iomem *phy_base)
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{
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u8 ck_step0, ck_step1; /* ckoffset_step for clock */
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u8 q_step; /* qoffset_step for clock */
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int dx;
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dx = 2; /* use dx2 in sLD11 */
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ck_step0 = ddrphy_hpstep(delay_ckoffset0, dx, phy_base); /* CK-Offset */
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ck_step1 = ddrphy_hpstep(delay_ckoffset1, dx, phy_base); /* CK-Offset */
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q_step = ddrphy_hpstep(delay_qoffset, dx, phy_base); /* Q-Offset */
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ddrphy_vt_ctrl(phy_base, 0);
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/* Q->[23:18], CK1->[11:6], CK0->bit[5:0] */
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if (enable == 1)
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ddrphy_maskwritel((q_step << 18) + (ck_step1 << 6) + ck_step0,
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PHY_ACBD_MASK | PHY_CK1BD_MASK | PHY_CK0BD_MASK,
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phy_base + PHY_ACBDLR);
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ddrphy_vt_ctrl(phy_base, 1);
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}
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static void ddrphy_set_wl_delay_dx(int dx, int r0_delay, int r1_delay,
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int enable, void __iomem *phy_base)
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{
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int rank;
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int delay_wl[4];
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u32 wl_mask = 0; /* WriteLeveling's Mask */
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u32 wl_value = 0; /* WriteLeveling's Value */
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delay_wl[0] = r0_delay & 0xfff;
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delay_wl[1] = r1_delay & 0xfff;
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delay_wl[2] = 0;
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delay_wl[3] = 0;
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ddrphy_vt_ctrl(phy_base, 0);
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for (rank = 0; rank < 4; rank++) {
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wl_mask |= PHY_WLD_MASK(rank);
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/* WriteLeveling's delay */
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wl_value |= ddrphy_hpstep(delay_wl[rank], dx, phy_base) << (8 * rank);
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}
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if (enable == 1)
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ddrphy_maskwritel(wl_value, wl_mask, phy_base + PHY_DXLCDLR0(dx));
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ddrphy_vt_ctrl(phy_base, 1);
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}
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static void ddrphy_set_dqsg_delay_dx(int dx, int r0_delay, int r1_delay,
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int enable, void __iomem *phy_base)
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{
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int rank;
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int delay_dqsg[4];
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u32 dqsg_mask = 0; /* DQSGating_LCDL_delay's Mask */
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u32 dqsg_value = 0; /* DQSGating_LCDL_delay's Value */
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delay_dqsg[0] = r0_delay;
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delay_dqsg[1] = r1_delay;
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delay_dqsg[2] = 0;
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delay_dqsg[3] = 0;
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ddrphy_vt_ctrl(phy_base, 0);
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for (rank = 0; rank < 4; rank++) {
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dqsg_mask |= PHY_DQSGD_MASK(rank);
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/* DQSGating's delay */
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dqsg_value |= ddrphy_hpstep(delay_dqsg[rank], dx, phy_base) << (8 * rank);
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}
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if (enable == 1)
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ddrphy_maskwritel(dqsg_value, dqsg_mask, phy_base + PHY_DXLCDLR2(dx));
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ddrphy_vt_ctrl(phy_base, 1);
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}
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static void ddrphy_set_dswb_delay_dx(int dx, int delay, int enable, void __iomem *phy_base)
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{
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u8 dswb_step;
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ddrphy_vt_ctrl(phy_base, 0);
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dswb_step = ddrphy_hpstep(delay, dx, phy_base); /* DQS-BDL's delay */
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if (enable == 1)
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ddrphy_maskwritel(dswb_step << 24, PHY_DSWBD_MASK, phy_base + PHY_DXBDLR1(dx));
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ddrphy_vt_ctrl(phy_base, 1);
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}
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static void ddrphy_set_oe_delay_dx(int dx, int dqs_delay, int dq_delay,
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int enable, void __iomem *phy_base)
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{
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u8 dqs_oe_step, dq_oe_step;
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u32 wdata;
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ddrphy_vt_ctrl(phy_base, 0);
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/* OE(DQS,DQ) */
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dqs_oe_step = ddrphy_hpstep(dqs_delay, dx, phy_base); /* DQS-oe's delay */
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dq_oe_step = ddrphy_hpstep(dq_delay, dx, phy_base); /* DQ-oe's delay */
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wdata = ((dq_oe_step<<6) + dqs_oe_step) & 0xFFF;
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if (enable == 1)
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ddrphy_maskwritel(wdata, PHY_DSDQOE_MASK, phy_base + PHY_DXBDLR2(dx));
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ddrphy_vt_ctrl(phy_base, 1);
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}
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static void ddrphy_ext_dqsgt(void __iomem *phy_base)
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{
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/* Extend DQSGating_window min:+1T max:+1T */
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ddrphy_maskwritel(PHY_DQSGX_MASK, PHY_DQSGX_MASK, phy_base + PHY_DSGCR);
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}
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static void ddrphy_shift_tof_hws(void __iomem *phy_base, const int shift[][2])
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{
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int dx, block, byte;
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u32 lcdlr1, wdqd;
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ddrphy_vt_ctrl(phy_base, 0);
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for (block = 0; block < RANK_BLOCKS_TR; block++) {
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for (byte = 0; byte < 2; byte++) {
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dx = block * 2 + byte;
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lcdlr1 = readl(phy_base + PHY_DXLCDLR1(dx));
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wdqd = lcdlr1 & 0xff;
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wdqd = clamp(wdqd + ddrphy_hpstep(shift[block][byte], dx, phy_base),
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0U, 0xffU);
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lcdlr1 = (lcdlr1 & ~0xff) | wdqd;
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writel(lcdlr1, phy_base + PHY_DXLCDLR1(dx));
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readl(phy_base + PHY_DXLCDLR1(dx)); /* relax */
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}
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}
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ddrphy_vt_ctrl(phy_base, 1);
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}
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static void ddrphy_shift_rof_hws(void __iomem *phy_base, const int pos_shift[][2],
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const int neg_shift[][2])
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{
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int dx, block, byte;
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u32 lcdlr1, rdqsd, rdqnsd;
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ddrphy_vt_ctrl(phy_base, 0);
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for (block = 0; block < RANK_BLOCKS_TR; block++) {
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for (byte = 0; byte < 2; byte++) {
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dx = block * 2 + byte;
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lcdlr1 = readl(phy_base + PHY_DXLCDLR1(dx));
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/* DQS LCDL RDQNSD->[23:16] RDQSD->[15:8] */
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rdqsd = (lcdlr1 >> 8) & 0xff;
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rdqnsd = (lcdlr1 >> 16) & 0xff;
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rdqsd = clamp(rdqsd + ddrphy_hpstep(pos_shift[block][byte], dx, phy_base),
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0U, 0xffU);
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rdqnsd = clamp(rdqnsd + ddrphy_hpstep(neg_shift[block][byte], dx, phy_base),
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0U, 0xffU);
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lcdlr1 = (lcdlr1 & ~(0xffff << 8)) | (rdqsd << 8) | (rdqnsd << 16);
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writel(lcdlr1, phy_base + PHY_DXLCDLR1(dx));
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readl(phy_base + PHY_DXLCDLR1(dx)); /* relax */
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}
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}
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ddrphy_vt_ctrl(phy_base, 1);
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}
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static void ddrphy_boot_run_hws(void __iomem *phy_base)
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{
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/* Hard Training for DIO */
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writel(0x0000f401, phy_base + PHY_PIR);
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while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
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cpu_relax();
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}
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static void ddrphy_training(void __iomem *phy_base)
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{
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/* DIO roffset shift before hard training */
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ddrphy_shift_rof_hws(phy_base, rof_pos_shift_pre, rof_neg_shift_pre);
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/* Hard Training for each CH */
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ddrphy_boot_run_hws(phy_base);
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/* DIO toffset shift after training */
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ddrphy_shift_tof_hws(phy_base, tof_shift);
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/* DIO roffset shift after training */
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ddrphy_shift_rof_hws(phy_base, rof_pos_shift, rof_neg_shift);
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/* Extend DQSGating window min:+1T max:+1T */
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ddrphy_ext_dqsgt(phy_base);
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}
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static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq)
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{
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writel(0x40000000, phy_base + PHY_PIR);
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writel(0x0300C4F1, phy_base + PHY_PGCR1);
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writel(0x0C807D04, phy_base + PHY_PTR0);
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writel(0x27100578, phy_base + PHY_PTR1);
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writel(0x00083DEF, phy_base + PHY_PTR2);
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writel(0x12061A80, phy_base + PHY_PTR3);
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writel(0x08027100, phy_base + PHY_PTR4);
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writel(0x9D9CBB66, phy_base + PHY_DTPR0);
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writel(0x1a878400, phy_base + PHY_DTPR1);
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writel(0x50025200, phy_base + PHY_DTPR2);
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writel(0xF004641A, phy_base + PHY_DSGCR);
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writel(0x0000040B, phy_base + PHY_DCR);
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writel(0x00000d71, phy_base + PHY_MR0);
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writel(0x00000006, phy_base + PHY_MR1);
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writel(0x00000098, phy_base + PHY_MR2);
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writel(0x00000000, phy_base + PHY_MR3);
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while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
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cpu_relax();
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writel(0x00000059, phy_base + PHY_ZQ0CR1);
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writel(0x00000019, phy_base + PHY_ZQ1CR1);
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writel(0x00000019, phy_base + PHY_ZQ2CR1);
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writel(0x30FC6C20, phy_base + PHY_PGCR2);
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ddrphy_set_ckoffset_qoffset(119, 0, 0, 1, phy_base);
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ddrphy_set_wl_delay_dx(0, 220, 220, 1, phy_base);
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ddrphy_set_wl_delay_dx(1, 160, 160, 1, phy_base);
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ddrphy_set_wl_delay_dx(2, 190, 190, 1, phy_base);
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ddrphy_set_wl_delay_dx(3, 150, 150, 1, phy_base);
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ddrphy_set_dqsg_delay_dx(0, 750, 750, 1, phy_base);
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ddrphy_set_dqsg_delay_dx(1, 750, 750, 1, phy_base);
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ddrphy_set_dqsg_delay_dx(2, 750, 750, 1, phy_base);
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ddrphy_set_dqsg_delay_dx(3, 750, 750, 1, phy_base);
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ddrphy_set_dswb_delay_dx(0, 0, 1, phy_base);
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ddrphy_set_dswb_delay_dx(1, 0, 1, phy_base);
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ddrphy_set_dswb_delay_dx(2, 0, 1, phy_base);
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ddrphy_set_dswb_delay_dx(3, 0, 1, phy_base);
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ddrphy_set_oe_delay_dx(0, 0, 0, 1, phy_base);
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ddrphy_set_oe_delay_dx(1, 0, 0, 1, phy_base);
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ddrphy_set_oe_delay_dx(2, 0, 0, 1, phy_base);
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ddrphy_set_oe_delay_dx(3, 0, 0, 1, phy_base);
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writel(0x44000E81, phy_base + PHY_DX0GCR);
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writel(0x44000E81, phy_base + PHY_DX1GCR);
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writel(0x44000E81, phy_base + PHY_DX2GCR);
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writel(0x44000E81, phy_base + PHY_DX3GCR);
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writel(0x00055002, phy_base + PHY_DX0GTR);
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writel(0x00055002, phy_base + PHY_DX1GTR);
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writel(0x00055010, phy_base + PHY_DX2GTR);
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writel(0x00055010, phy_base + PHY_DX3GTR);
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writel(0x930035C7, phy_base + PHY_DTCR);
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writel(0x00000003, phy_base + PHY_PIR);
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readl(phy_base + PHY_PIR);
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while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
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cpu_relax();
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writel(0x00000181, phy_base + PHY_PIR);
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readl(phy_base + PHY_PIR);
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while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
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cpu_relax();
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writel(0x44181884, phy_base + PHY_DXCCR);
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writel(0x00000001, phy_base + PHY_GPR1);
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}
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/* UMC */
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static const u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060B0B1C};
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static const u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x27201806};
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static const u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00120B04};
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static const u32 umc_cmdctle[DRAM_FREQ_NR] = {0x00680607};
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static const u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200};
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static const u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808};
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static const u32 umc_rdatactl[DRAM_FREQ_NR] = {0x00000810};
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static const u32 umc_wdatactl[DRAM_FREQ_NR] = {0x00000004};
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static const u32 umc_odtctl[DRAM_FREQ_NR] = {0x02000002};
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static const u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203};
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static const u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605};
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static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
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unsigned long size, int ch)
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{
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/* Wait for PHY Init Complete */
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writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
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writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
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writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
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writel(umc_cmdctle[freq], dc_base + UMC_CMDCTLE);
|
|
writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF);
|
|
writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG);
|
|
|
|
writel(umc_rdatactl[freq], dc_base + UMC_RDATACTL_D0);
|
|
writel(umc_rdatactl[freq], dc_base + UMC_RDATACTL_D1);
|
|
|
|
writel(umc_wdatactl[freq], dc_base + UMC_WDATACTL_D0);
|
|
writel(umc_wdatactl[freq], dc_base + UMC_WDATACTL_D1);
|
|
|
|
writel(umc_odtctl[freq], dc_base + UMC_ODTCTL_D0);
|
|
writel(umc_odtctl[freq], dc_base + UMC_ODTCTL_D1);
|
|
|
|
writel(0x00000003, dc_base + UMC_ACSSETA);
|
|
writel(0x00000103, dc_base + UMC_FLOWCTLG);
|
|
writel(umc_acssetb[ch], dc_base + UMC_ACSSETB);
|
|
writel(0x02020200, dc_base + UMC_SPCSETB);
|
|
writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
|
|
writel(0x00000002, dc_base + UMC_ACFETCHCTRL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int umc_ch_init(void __iomem *umc_ch_base,
|
|
enum dram_freq freq, unsigned long size, int ch)
|
|
{
|
|
void __iomem *dc_base = umc_ch_base;
|
|
|
|
return umc_dc_init(dc_base, freq, size, ch);
|
|
}
|
|
|
|
static void um_init(void __iomem *um_base)
|
|
{
|
|
writel(0x00000001, um_base + UMC_SIORST);
|
|
writel(0x00000001, um_base + UMC_VO0RST);
|
|
writel(0x00000001, um_base + UMC_VPERST);
|
|
writel(0x00000001, um_base + UMC_RGLRST);
|
|
writel(0x00000001, um_base + UMC_A2DRST);
|
|
writel(0x00000001, um_base + UMC_DMDRST);
|
|
}
|
|
|
|
int uniphier_ld11_umc_init(const struct uniphier_board_data *bd)
|
|
{
|
|
void __iomem *um_base = (void __iomem *)0x5B800000;
|
|
void __iomem *umc_ch_base = (void __iomem *)0x5BC00000;
|
|
void __iomem *phy_base = (void __iomem *)0x5BC01000;
|
|
enum dram_freq freq;
|
|
int ch, ret;
|
|
|
|
switch (bd->dram_freq) {
|
|
case 1600:
|
|
freq = DRAM_FREQ_1600M;
|
|
break;
|
|
default:
|
|
pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
|
|
return -EINVAL;
|
|
}
|
|
|
|
writel(0x00000101, umc_ch_base + UMC_DIOCTLA);
|
|
while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
|
|
cpu_relax();
|
|
|
|
writel(0x00000000, umc_ch_base + UMC_DIOCTLA);
|
|
writel(0x00000001, umc_ch_base + UMC_DEBUGC);
|
|
writel(0x00000101, umc_ch_base + UMC_DIOCTLA);
|
|
|
|
writel(0x00000100, umc_ch_base + UMC_INITSET);
|
|
while (readl(umc_ch_base + UMC_INITSTAT) & BIT(8))
|
|
cpu_relax();
|
|
|
|
writel(0x00000100, umc_ch_base + 0x00200000 + UMC_INITSET);
|
|
while (readl(umc_ch_base + 0x00200000 + UMC_INITSTAT) & BIT(8))
|
|
cpu_relax();
|
|
|
|
ddrphy_init(phy_base, freq);
|
|
|
|
for (ch = 0; ch < DRAM_CH_NR; ch++) {
|
|
unsigned long size = bd->dram_ch[ch].size;
|
|
unsigned int width = bd->dram_ch[ch].width;
|
|
|
|
ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), ch);
|
|
if (ret) {
|
|
pr_err("failed to initialize UMC ch%d\n", ch);
|
|
return ret;
|
|
}
|
|
|
|
umc_ch_base += 0x00200000;
|
|
}
|
|
ddrphy_training(phy_base);
|
|
|
|
um_init(um_base);
|
|
|
|
return 0;
|
|
}
|