mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-06 13:14:27 +00:00
159e7a224d
This reverts commit 2a5d5d27ed.
The commit breaks uboot boot (hang in ddr init)
on many PowerPC boards like P3041DS, P4080DS
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
552 lines
17 KiB
C
552 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2008-2012 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/processor.h>
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#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
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#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
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#endif
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/*
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* regs has the to-be-set values for DDR controller registers
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* ctrl_num is the DDR controller number
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* step: 0 goes through the initialization in one pass
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* 1 sets registers and returns before enabling controller
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* 2 resumes from step 1 and continues to initialize
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* Dividing the initialization to two steps to deassert DDR reset signal
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* to comply with JEDEC specs for RDIMMs.
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*/
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void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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unsigned int ctrl_num, int step)
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{
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unsigned int i, bus_width;
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struct ccsr_ddr __iomem *ddr;
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u32 temp_sdram_cfg;
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u32 total_gb_size_per_controller;
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int timeout;
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
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int timeout_save;
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volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
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unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
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int csn = -1;
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
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u32 save1, save2;
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#endif
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switch (ctrl_num) {
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case 0:
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ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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break;
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#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
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case 1:
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ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
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break;
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#endif
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#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
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case 2:
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ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
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break;
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#endif
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#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
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case 3:
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ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
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break;
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#endif
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default:
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printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
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return;
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}
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if (step == 2)
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goto step2;
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if (regs->ddr_eor)
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out_be32(&ddr->eor, regs->ddr_eor);
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
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debug("Workaround for ERRATUM_DDR111_DDR134\n");
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
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cs_ea = regs->cs[i].bnds & 0xfff;
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if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
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csn = i;
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csn_bnds_backup = regs->cs[i].bnds;
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csn_bnds_t = (unsigned int *) ®s->cs[i].bnds;
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if (cs_ea > 0xeff)
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*csn_bnds_t = regs->cs[i].bnds + 0x01000000;
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else
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*csn_bnds_t = regs->cs[i].bnds + 0x01000100;
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debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
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"change it to 0x%x\n",
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csn, csn_bnds_backup, regs->cs[i].bnds);
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break;
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}
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}
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#endif
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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if (i == 0) {
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out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs0_config, regs->cs[i].config);
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out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
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} else if (i == 1) {
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out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs1_config, regs->cs[i].config);
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out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
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} else if (i == 2) {
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out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs2_config, regs->cs[i].config);
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out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
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} else if (i == 3) {
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out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs3_config, regs->cs[i].config);
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out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
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}
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}
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out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
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out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
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out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
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out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
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out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
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out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
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out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
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out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
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out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
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out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
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out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
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out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
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out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
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out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
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out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
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out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
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out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
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out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
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out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
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out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
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#ifndef CONFIG_SYS_FSL_DDR_EMU
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/*
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* Skip these two registers if running on emulator
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* because emulator doesn't have skew between bytes.
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*/
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if (regs->ddr_wrlvl_cntl_2)
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out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
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if (regs->ddr_wrlvl_cntl_3)
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out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
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#endif
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out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
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out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
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out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
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out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
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#ifdef CONFIG_DEEP_SLEEP
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if (is_warm_boot()) {
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out_be32(&ddr->sdram_cfg_2,
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regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
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out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
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out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
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/* DRAM VRef will not be trained */
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out_be32(&ddr->ddr_cdr2,
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regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
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} else
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#endif
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{
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out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
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out_be32(&ddr->init_addr, regs->ddr_init_addr);
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out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
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out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
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}
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out_be32(&ddr->err_disable, regs->err_disable);
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out_be32(&ddr->err_int_en, regs->err_int_en);
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for (i = 0; i < 32; i++) {
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if (regs->debug[i]) {
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debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
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out_be32(&ddr->debug[i], regs->debug[i]);
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}
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}
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
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out_be32(&ddr->debug[12], 0x00000015);
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out_be32(&ddr->debug[21], 0x24000000);
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#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
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/*
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* For RDIMMs, JEDEC spec requires clocks to be stable before reset is
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* deasserted. Clocks start when any chip select is enabled and clock
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* control register is set. Because all DDR components are connected to
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* one reset signal, this needs to be done in two steps. Step 1 is to
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* get the clocks started. Step 2 resumes after reset signal is
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* deasserted.
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*/
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if (step == 1) {
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udelay(200);
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return;
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}
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step2:
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/* Set, but do not enable the memory */
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temp_sdram_cfg = regs->ddr_sdram_cfg;
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temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
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out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
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debug("Workaround for ERRATUM_DDR_A003\n");
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if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
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out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
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out_be32(&ddr->debug[2], 0x00000400);
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out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
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out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
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out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
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out_be32(&ddr->mtcr, 0);
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save1 = in_be32(&ddr->debug[12]);
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save2 = in_be32(&ddr->debug[21]);
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out_be32(&ddr->debug[12], 0x00000015);
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out_be32(&ddr->debug[21], 0x24000000);
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out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
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out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
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asm volatile("sync;isync");
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while (!(in_be32(&ddr->debug[1]) & 0x2))
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;
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switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
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case 0x00000000:
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out_be32(&ddr->sdram_md_cntl,
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MD_CNTL_MD_EN |
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MD_CNTL_CS_SEL_CS0_CS1 |
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0x04000000 |
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MD_CNTL_WRCW |
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MD_CNTL_MD_VALUE(0x02));
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#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
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if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
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break;
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while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
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;
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out_be32(&ddr->sdram_md_cntl,
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MD_CNTL_MD_EN |
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MD_CNTL_CS_SEL_CS2_CS3 |
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0x04000000 |
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MD_CNTL_WRCW |
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MD_CNTL_MD_VALUE(0x02));
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#endif
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break;
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case 0x00100000:
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out_be32(&ddr->sdram_md_cntl,
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MD_CNTL_MD_EN |
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MD_CNTL_CS_SEL_CS0_CS1 |
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0x04000000 |
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MD_CNTL_WRCW |
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MD_CNTL_MD_VALUE(0x0a));
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#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
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if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
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break;
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while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
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;
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out_be32(&ddr->sdram_md_cntl,
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MD_CNTL_MD_EN |
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MD_CNTL_CS_SEL_CS2_CS3 |
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0x04000000 |
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MD_CNTL_WRCW |
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MD_CNTL_MD_VALUE(0x0a));
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#endif
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break;
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case 0x00200000:
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out_be32(&ddr->sdram_md_cntl,
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MD_CNTL_MD_EN |
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MD_CNTL_CS_SEL_CS0_CS1 |
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0x04000000 |
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MD_CNTL_WRCW |
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MD_CNTL_MD_VALUE(0x12));
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#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
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if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
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break;
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while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
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;
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out_be32(&ddr->sdram_md_cntl,
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MD_CNTL_MD_EN |
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MD_CNTL_CS_SEL_CS2_CS3 |
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0x04000000 |
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MD_CNTL_WRCW |
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MD_CNTL_MD_VALUE(0x12));
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#endif
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break;
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case 0x00300000:
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out_be32(&ddr->sdram_md_cntl,
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MD_CNTL_MD_EN |
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MD_CNTL_CS_SEL_CS0_CS1 |
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0x04000000 |
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MD_CNTL_WRCW |
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MD_CNTL_MD_VALUE(0x1a));
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#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
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if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
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break;
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while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
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;
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out_be32(&ddr->sdram_md_cntl,
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MD_CNTL_MD_EN |
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MD_CNTL_CS_SEL_CS2_CS3 |
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0x04000000 |
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MD_CNTL_WRCW |
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MD_CNTL_MD_VALUE(0x1a));
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#endif
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break;
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default:
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out_be32(&ddr->sdram_md_cntl,
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MD_CNTL_MD_EN |
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MD_CNTL_CS_SEL_CS0_CS1 |
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0x04000000 |
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MD_CNTL_WRCW |
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MD_CNTL_MD_VALUE(0x02));
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#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
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if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
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break;
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while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
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;
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out_be32(&ddr->sdram_md_cntl,
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MD_CNTL_MD_EN |
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MD_CNTL_CS_SEL_CS2_CS3 |
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0x04000000 |
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MD_CNTL_WRCW |
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MD_CNTL_MD_VALUE(0x02));
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#endif
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printf("Unsupported RC10\n");
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break;
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}
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while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
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;
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udelay(6);
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out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
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out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
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out_be32(&ddr->debug[2], 0x0);
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out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
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out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
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out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
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out_be32(&ddr->debug[12], save1);
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out_be32(&ddr->debug[21], save2);
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out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
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}
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#endif
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/*
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* For 8572 DDR1 erratum - DDR controller may enter illegal state
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* when operatiing in 32-bit bus mode with 4-beat bursts,
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* This erratum does not affect DDR3 mode, only for DDR2 mode.
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*/
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
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debug("Workaround for ERRATUM_DDR_115\n");
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if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
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&& in_be32(&ddr->sdram_cfg) & 0x80000) {
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/* set DEBUG_1[31] */
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setbits_be32(&ddr->debug[0], 1);
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}
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
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debug("Workaround for ERRATUM_DDR111_DDR134\n");
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/*
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* This is the combined workaround for DDR111 and DDR134
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* following the published errata for MPC8572
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*/
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/* 1. Set EEBACR[3] */
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setbits_be32(&ecm->eebacr, 0x10000000);
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debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
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/* 2. Set DINIT in SDRAM_CFG_2*/
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setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
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debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
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in_be32(&ddr->sdram_cfg_2));
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/* 3. Set DEBUG_3[21] */
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setbits_be32(&ddr->debug[2], 0x400);
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debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
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#endif /* part 1 of the workaound */
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/*
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* 500 painful micro-seconds must elapse between
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* the DDR clock setup and the DDR config enable.
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* DDR2 need 200 us, and DDR3 need 500 us from spec,
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* we choose the max, that is 500 us for all of case.
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*/
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udelay(500);
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asm volatile("sync;isync");
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#ifdef CONFIG_DEEP_SLEEP
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if (is_warm_boot()) {
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/* enter self-refresh */
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setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
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|
/* do board specific memory setup */
|
|
board_mem_sleep_setup();
|
|
temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
|
|
} else
|
|
#endif
|
|
temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI);
|
|
|
|
/* Let the controller go */
|
|
out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
|
|
asm volatile("sync;isync");
|
|
|
|
total_gb_size_per_controller = 0;
|
|
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
|
|
if (!(regs->cs[i].config & 0x80000000))
|
|
continue;
|
|
total_gb_size_per_controller += 1 << (
|
|
((regs->cs[i].config >> 14) & 0x3) + 2 +
|
|
((regs->cs[i].config >> 8) & 0x7) + 12 +
|
|
((regs->cs[i].config >> 0) & 0x7) + 8 +
|
|
3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
|
|
26); /* minus 26 (count of 64M) */
|
|
}
|
|
if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */
|
|
total_gb_size_per_controller *= 3;
|
|
else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
|
|
total_gb_size_per_controller <<= 1;
|
|
/*
|
|
* total memory / bus width = transactions needed
|
|
* transactions needed / data rate = seconds
|
|
* to add plenty of buffer, double the time
|
|
* For example, 2GB on 666MT/s 64-bit bus takes about 402ms
|
|
* Let's wait for 800ms
|
|
*/
|
|
bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
|
|
>> SDRAM_CFG_DBW_SHIFT);
|
|
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
|
|
(get_ddr_freq(ctrl_num) >> 20)) << 1;
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
|
|
timeout_save = timeout;
|
|
#endif
|
|
total_gb_size_per_controller >>= 4; /* shift down to gb size */
|
|
debug("total %d GB\n", total_gb_size_per_controller);
|
|
debug("Need to wait up to %d * 10ms\n", timeout);
|
|
|
|
/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
|
|
while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
|
|
(timeout >= 0)) {
|
|
udelay(10000); /* throttle polling rate */
|
|
timeout--;
|
|
}
|
|
|
|
if (timeout <= 0)
|
|
printf("Waiting for D_INIT timeout. Memory may not work.\n");
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
|
|
/* continue this workaround */
|
|
|
|
/* 4. Clear DEBUG3[21] */
|
|
clrbits_be32(&ddr->debug[2], 0x400);
|
|
debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
|
|
|
|
/* DDR134 workaround starts */
|
|
/* A: Clear sdram_cfg_2[odt_cfg] */
|
|
clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
|
|
debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
|
|
in_be32(&ddr->sdram_cfg_2));
|
|
|
|
/* B: Set DEBUG1[15] */
|
|
setbits_be32(&ddr->debug[0], 0x10000);
|
|
debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
|
|
|
|
/* C: Set timing_cfg_2[cpo] to 0b11111 */
|
|
setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
|
|
debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
|
|
in_be32(&ddr->timing_cfg_2));
|
|
|
|
/* D: Set D6 to 0x9f9f9f9f */
|
|
out_be32(&ddr->debug[5], 0x9f9f9f9f);
|
|
debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
|
|
|
|
/* E: Set D7 to 0x9f9f9f9f */
|
|
out_be32(&ddr->debug[6], 0x9f9f9f9f);
|
|
debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
|
|
|
|
/* F: Set D2[20] */
|
|
setbits_be32(&ddr->debug[1], 0x800);
|
|
debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
|
|
|
|
/* G: Poll on D2[20] until cleared */
|
|
while (in_be32(&ddr->debug[1]) & 0x800)
|
|
udelay(10000); /* throttle polling rate */
|
|
|
|
/* H: Clear D1[15] */
|
|
clrbits_be32(&ddr->debug[0], 0x10000);
|
|
debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
|
|
|
|
/* I: Set sdram_cfg_2[odt_cfg] */
|
|
setbits_be32(&ddr->sdram_cfg_2,
|
|
regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
|
|
debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
|
|
|
|
/* Continuing with the DDR111 workaround */
|
|
/* 5. Set D2[21] */
|
|
setbits_be32(&ddr->debug[1], 0x400);
|
|
debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
|
|
|
|
/* 6. Poll D2[21] until its cleared */
|
|
while (in_be32(&ddr->debug[1]) & 0x400)
|
|
udelay(10000); /* throttle polling rate */
|
|
|
|
/* 7. Wait for state machine 2nd run, roughly 400ms/GB */
|
|
debug("Wait for %d * 10ms\n", timeout_save);
|
|
udelay(timeout_save * 10000);
|
|
|
|
/* 8. Set sdram_cfg_2[dinit] if options requires */
|
|
setbits_be32(&ddr->sdram_cfg_2,
|
|
regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
|
|
debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
|
|
|
|
/* 9. Poll until dinit is cleared */
|
|
timeout = timeout_save;
|
|
debug("Need to wait up to %d * 10ms\n", timeout);
|
|
while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
|
|
(timeout >= 0)) {
|
|
udelay(10000); /* throttle polling rate */
|
|
timeout--;
|
|
}
|
|
|
|
if (timeout <= 0)
|
|
printf("Waiting for D_INIT timeout. Memory may not work.\n");
|
|
|
|
/* 10. Clear EEBACR[3] */
|
|
clrbits_be32(&ecm->eebacr, 10000000);
|
|
debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
|
|
|
|
if (csn != -1) {
|
|
csn_bnds_t = (unsigned int *) ®s->cs[csn].bnds;
|
|
*csn_bnds_t = csn_bnds_backup;
|
|
debug("Change cs%d_bnds back to 0x%08x\n",
|
|
csn, regs->cs[csn].bnds);
|
|
setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */
|
|
switch (csn) {
|
|
case 0:
|
|
out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
|
|
break;
|
|
case 1:
|
|
out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
|
|
break;
|
|
#if CONFIG_CHIP_SELECTS_PER_CTRL > 2
|
|
case 2:
|
|
out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
|
|
break;
|
|
case 3:
|
|
out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
|
|
break;
|
|
#endif
|
|
}
|
|
clrbits_be32(&ddr->sdram_cfg, 0x2);
|
|
}
|
|
#endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
|
|
#ifdef CONFIG_DEEP_SLEEP
|
|
if (is_warm_boot())
|
|
/* exit self-refresh */
|
|
clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
|
|
#endif
|
|
}
|