u-boot/arch/arm/dts/rk3328-u-boot.dtsi
Chen-Yu Tsai 32fd6169a1 rockchip: dts: rk3328: Move OTG node's hnp-srp-disable to rk3328-u-boot.dtsi
The "hnp-srp-disable" property for dwc2 is specific to U-boot, not part
of upstream Linux's device tree bindings.

Move it to rk3328-u-boot.dtsi to avoid losing it when syncing device
tree files.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-01 18:32:56 +08:00

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1.2 KiB
Text

// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
/ {
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc;
};
chosen {
u-boot,spl-boot-order = &emmc, &sdmmc;
};
dmc: dmc {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3328-dmc";
reg = <0x0 0xff400000 0x0 0x1000
0x0 0xff780000 0x0 0x3000
0x0 0xff100000 0x0 0x1000
0x0 0xff440000 0x0 0x1000
0x0 0xff720000 0x0 0x1000
0x0 0xff798000 0x0 0x1000>;
};
usb_host0_xhci: usb@ff600000 {
compatible = "rockchip,rk3328-xhci";
reg = <0x0 0xff600000 0x0 0x100000>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
snps,dis-enblslpm-quirk;
snps,phyif-utmi-bits = <16>;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-u2-susphy-quirk;
status = "disabled";
};
};
&cru {
u-boot,dm-pre-reloc;
};
&grf {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
clock-frequency = <24000000>;
};
&emmc {
u-boot,dm-pre-reloc;
/* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
u-boot,spl-fifo-mode;
};
&sdmmc {
u-boot,dm-pre-reloc;
/* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
u-boot,spl-fifo-mode;
};
&usb20_otg {
hnp-srp-disable;
};