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add396d667
Register mii_bus with read and write callbacks to allow the 'mii' command to work. Use a timeout of 10 ms to wait for the R/W operations to complete. Signed-off-by: Sergei Antonov <saproj@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Rick Chen <rick@andestech.com>
464 lines
10 KiB
C
464 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Faraday FTMAC100 Ethernet
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*
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* (C) Copyright 2009 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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*/
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#include <config.h>
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#include <common.h>
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#include <cpu_func.h>
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#include <env.h>
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#include <malloc.h>
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#include <net.h>
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#include <phy.h>
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#include <miiphy.h>
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#include <dm/device_compat.h>
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#include <asm/global_data.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include "ftmac100.h"
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#include <dm.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define ETH_ZLEN 60
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/* Timeout for a mdio read/write operation */
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#define FTMAC100_MDIO_TIMEOUT_USEC 10000
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struct ftmac100_data {
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struct ftmac100_txdes txdes[1];
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struct ftmac100_rxdes rxdes[PKTBUFSRX];
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int rx_index;
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const char *name;
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struct ftmac100 *ftmac100;
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struct mii_dev *bus;
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};
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/*
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* Reset MAC
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*/
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static void ftmac100_reset(struct ftmac100_data *priv)
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{
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struct ftmac100 *ftmac100 = priv->ftmac100;
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debug ("%s()\n", __func__);
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writel (FTMAC100_MACCR_SW_RST, &ftmac100->maccr);
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while (readl (&ftmac100->maccr) & FTMAC100_MACCR_SW_RST)
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mdelay(1);
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/*
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* When soft reset complete, write mac address immediately maybe fail somehow
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* Wait for a while can avoid this problem
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*/
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mdelay(1);
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}
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/*
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* Set MAC address
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*/
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static void ftmac100_set_mac(struct ftmac100_data *priv ,
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const unsigned char *mac)
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{
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struct ftmac100 *ftmac100 = priv->ftmac100;
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unsigned int maddr = mac[0] << 8 | mac[1];
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unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
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debug ("%s(%x %x)\n", __func__, maddr, laddr);
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writel (maddr, &ftmac100->mac_madr);
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writel (laddr, &ftmac100->mac_ladr);
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}
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/*
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* Disable MAC
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*/
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static void _ftmac100_halt(struct ftmac100_data *priv)
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{
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struct ftmac100 *ftmac100 = priv->ftmac100;
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debug ("%s()\n", __func__);
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writel (0, &ftmac100->maccr);
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}
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/*
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* Initialize MAC
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*/
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static int _ftmac100_init(struct ftmac100_data *priv, unsigned char enetaddr[6])
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{
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struct ftmac100 *ftmac100 = priv->ftmac100;
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struct ftmac100_txdes *txdes = priv->txdes;
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struct ftmac100_rxdes *rxdes = priv->rxdes;
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unsigned int maccr;
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int i;
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debug ("%s()\n", __func__);
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ftmac100_reset(priv);
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/* set the ethernet address */
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ftmac100_set_mac(priv, enetaddr);
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/* disable all interrupts */
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writel (0, &ftmac100->imr);
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/* initialize descriptors */
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priv->rx_index = 0;
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txdes[0].txdes1 = FTMAC100_TXDES1_EDOTR;
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rxdes[PKTBUFSRX - 1].rxdes1 = FTMAC100_RXDES1_EDORR;
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for (i = 0; i < PKTBUFSRX; i++) {
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/* RXBUF_BADR */
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rxdes[i].rxdes2 = (unsigned int)(unsigned long)net_rx_packets[i];
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rxdes[i].rxdes1 |= FTMAC100_RXDES1_RXBUF_SIZE (PKTSIZE_ALIGN);
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rxdes[i].rxdes0 = FTMAC100_RXDES0_RXDMA_OWN;
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}
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/* transmit ring */
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writel ((unsigned long)txdes, &ftmac100->txr_badr);
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/* receive ring */
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writel ((unsigned long)rxdes, &ftmac100->rxr_badr);
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/* poll receive descriptor automatically */
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writel (FTMAC100_APTC_RXPOLL_CNT (1), &ftmac100->aptc);
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/* enable transmitter, receiver */
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maccr = FTMAC100_MACCR_XMT_EN |
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FTMAC100_MACCR_RCV_EN |
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FTMAC100_MACCR_XDMA_EN |
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FTMAC100_MACCR_RDMA_EN |
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FTMAC100_MACCR_CRC_APD |
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FTMAC100_MACCR_ENRX_IN_HALFTX |
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FTMAC100_MACCR_RX_RUNT |
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FTMAC100_MACCR_RX_BROADPKT;
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writel (maccr, &ftmac100->maccr);
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return 0;
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}
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/*
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* Free receiving buffer
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*/
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static int _ftmac100_free_pkt(struct ftmac100_data *priv)
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{
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struct ftmac100_rxdes *curr_des;
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curr_des = &priv->rxdes[priv->rx_index];
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/* release buffer to DMA */
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curr_des->rxdes0 |= FTMAC100_RXDES0_RXDMA_OWN;
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priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
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return 0;
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}
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/*
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* Receive a data block via Ethernet
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*/
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static int __ftmac100_recv(struct ftmac100_data *priv)
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{
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struct ftmac100_rxdes *curr_des;
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unsigned short rxlen;
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curr_des = &priv->rxdes[priv->rx_index];
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if (curr_des->rxdes0 & FTMAC100_RXDES0_RXDMA_OWN)
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return 0;
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if (curr_des->rxdes0 & (FTMAC100_RXDES0_RX_ERR |
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FTMAC100_RXDES0_CRC_ERR |
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FTMAC100_RXDES0_FTL |
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FTMAC100_RXDES0_RUNT |
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FTMAC100_RXDES0_RX_ODD_NB)) {
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return 0;
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}
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rxlen = FTMAC100_RXDES0_RFL (curr_des->rxdes0);
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invalidate_dcache_range(curr_des->rxdes2,curr_des->rxdes2+rxlen);
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debug ("%s(): RX buffer %d, %x received\n",
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__func__, priv->rx_index, rxlen);
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return rxlen;
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}
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/*
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* Send a data block via Ethernet
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*/
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static int _ftmac100_send(struct ftmac100_data *priv, void *packet, int length)
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{
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struct ftmac100 *ftmac100 = priv->ftmac100;
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struct ftmac100_txdes *curr_des = priv->txdes;
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ulong start;
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if (curr_des->txdes0 & FTMAC100_TXDES0_TXDMA_OWN) {
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debug ("%s(): no TX descriptor available\n", __func__);
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return -1;
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}
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debug ("%s(%lx, %x)\n", __func__, (unsigned long)packet, length);
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length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
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/* initiate a transmit sequence */
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flush_dcache_range((unsigned long)packet,(unsigned long)packet+length);
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curr_des->txdes2 = (unsigned int)(unsigned long)packet; /* TXBUF_BADR */
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curr_des->txdes1 &= FTMAC100_TXDES1_EDOTR;
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curr_des->txdes1 |= FTMAC100_TXDES1_FTS |
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FTMAC100_TXDES1_LTS |
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FTMAC100_TXDES1_TXBUF_SIZE (length);
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curr_des->txdes0 = FTMAC100_TXDES0_TXDMA_OWN;
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/* start transmit */
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writel (1, &ftmac100->txpd);
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/* wait for transfer to succeed */
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start = get_timer(0);
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while (curr_des->txdes0 & FTMAC100_TXDES0_TXDMA_OWN) {
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if (get_timer(start) >= 5) {
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debug ("%s(): timed out\n", __func__);
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return -1;
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}
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}
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debug ("%s(): packet sent\n", __func__);
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return 0;
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}
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static int ftmac100_start(struct udevice *dev)
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{
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struct eth_pdata *plat = dev_get_plat(dev);
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struct ftmac100_data *priv = dev_get_priv(dev);
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return _ftmac100_init(priv, plat->enetaddr);
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}
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static void ftmac100_stop(struct udevice *dev)
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{
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struct ftmac100_data *priv = dev_get_priv(dev);
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_ftmac100_halt(priv);
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}
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static int ftmac100_send(struct udevice *dev, void *packet, int length)
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{
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struct ftmac100_data *priv = dev_get_priv(dev);
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int ret;
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ret = _ftmac100_send(priv , packet , length);
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return ret ? 0 : -ETIMEDOUT;
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}
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static int ftmac100_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct ftmac100_data *priv = dev_get_priv(dev);
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struct ftmac100_rxdes *curr_des;
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curr_des = &priv->rxdes[priv->rx_index];
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int len;
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len = __ftmac100_recv(priv);
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if (len)
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*packetp = (uchar *)(unsigned long)curr_des->rxdes2;
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return len ? len : -EAGAIN;
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}
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static int ftmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
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{
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struct ftmac100_data *priv = dev_get_priv(dev);
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_ftmac100_free_pkt(priv);
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return 0;
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}
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int ftmac100_read_rom_hwaddr(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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eth_env_get_enetaddr("ethaddr", pdata->enetaddr);
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return 0;
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}
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static const char *dtbmacaddr(u32 ifno)
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{
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int node, len;
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char enet[16];
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const char *mac;
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const char *path;
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if (gd->fdt_blob == NULL) {
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printf("%s: don't have a valid gd->fdt_blob!\n", __func__);
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return NULL;
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}
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node = fdt_path_offset(gd->fdt_blob, "/aliases");
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if (node < 0)
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return NULL;
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sprintf(enet, "ethernet%d", ifno);
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path = fdt_getprop(gd->fdt_blob, node, enet, NULL);
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if (!path) {
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printf("no alias for %s\n", enet);
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return NULL;
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}
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node = fdt_path_offset(gd->fdt_blob, path);
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mac = fdt_getprop(gd->fdt_blob, node, "mac-address", &len);
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if (mac && is_valid_ethaddr((u8 *)mac))
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return mac;
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return NULL;
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}
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static int ftmac100_of_to_plat(struct udevice *dev)
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{
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struct ftmac100_data *priv = dev_get_priv(dev);
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struct eth_pdata *pdata = dev_get_plat(dev);
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const char *mac;
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pdata->iobase = dev_read_addr(dev);
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priv->ftmac100 = phys_to_virt(pdata->iobase);
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mac = dtbmacaddr(0);
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if (mac)
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memcpy(pdata->enetaddr , mac , 6);
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return 0;
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}
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/*
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* struct mii_bus functions
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*/
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static int ftmac100_mdio_read(struct mii_dev *bus, int addr, int devad,
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int reg)
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{
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struct ftmac100_data *priv = bus->priv;
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struct ftmac100 *ftmac100 = priv->ftmac100;
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int phycr = FTMAC100_PHYCR_PHYAD(addr) |
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FTMAC100_PHYCR_REGAD(reg) |
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FTMAC100_PHYCR_MIIRD;
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int ret;
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writel(phycr, &ftmac100->phycr);
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ret = readl_poll_timeout(&ftmac100->phycr, phycr,
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!(phycr & FTMAC100_PHYCR_MIIRD),
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FTMAC100_MDIO_TIMEOUT_USEC);
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if (ret)
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pr_err("%s: mdio read failed (addr=0x%x reg=0x%x)\n",
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bus->name, addr, reg);
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else
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ret = phycr & FTMAC100_PHYCR_MIIRDATA;
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return ret;
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}
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static int ftmac100_mdio_write(struct mii_dev *bus, int addr, int devad,
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int reg, u16 value)
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{
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struct ftmac100_data *priv = bus->priv;
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struct ftmac100 *ftmac100 = priv->ftmac100;
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int phycr = FTMAC100_PHYCR_PHYAD(addr) |
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FTMAC100_PHYCR_REGAD(reg) |
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FTMAC100_PHYCR_MIIWR;
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int ret;
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writel(value, &ftmac100->phywdata);
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writel(phycr, &ftmac100->phycr);
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ret = readl_poll_timeout(&ftmac100->phycr, phycr,
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!(phycr & FTMAC100_PHYCR_MIIWR),
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FTMAC100_MDIO_TIMEOUT_USEC);
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if (ret)
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pr_err("%s: mdio write failed (addr=0x%x reg=0x%x)\n",
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bus->name, addr, reg);
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return ret;
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}
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static int ftmac100_mdio_init(struct udevice *dev)
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{
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struct ftmac100_data *priv = dev_get_priv(dev);
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struct mii_dev *bus;
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int ret;
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bus = mdio_alloc();
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if (!bus)
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return -ENOMEM;
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bus->read = ftmac100_mdio_read;
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bus->write = ftmac100_mdio_write;
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bus->priv = priv;
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ret = mdio_register_seq(bus, dev_seq(dev));
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if (ret) {
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mdio_free(bus);
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return ret;
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}
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priv->bus = bus;
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return 0;
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}
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static int ftmac100_probe(struct udevice *dev)
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{
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struct ftmac100_data *priv = dev_get_priv(dev);
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priv->name = dev->name;
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int ret = 0;
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ret = ftmac100_mdio_init(dev);
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if (ret) {
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dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
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goto out;
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}
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out:
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return ret;
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}
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static int ftmac100_remove(struct udevice *dev)
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{
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struct ftmac100_data *priv = dev_get_priv(dev);
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mdio_unregister(priv->bus);
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mdio_free(priv->bus);
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return 0;
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}
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static int ftmac100_bind(struct udevice *dev)
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{
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return device_set_name(dev, dev->name);
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}
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static const struct eth_ops ftmac100_ops = {
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.start = ftmac100_start,
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.send = ftmac100_send,
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.recv = ftmac100_recv,
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.stop = ftmac100_stop,
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.free_pkt = ftmac100_free_pkt,
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};
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static const struct udevice_id ftmac100_ids[] = {
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{ .compatible = "andestech,atmac100" },
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{ }
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};
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U_BOOT_DRIVER(ftmac100) = {
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.name = "ftmac100",
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.id = UCLASS_ETH,
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.of_match = ftmac100_ids,
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.bind = ftmac100_bind,
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.of_to_plat = ftmac100_of_to_plat,
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.probe = ftmac100_probe,
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.remove = ftmac100_remove,
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.ops = &ftmac100_ops,
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.priv_auto = sizeof(struct ftmac100_data),
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.plat_auto = sizeof(struct eth_pdata),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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