u-boot/drivers/clk/rockchip
Vasily Khoruzhick 4340771323 clk: rockchip: rk3568: add stubs for CLK_PCIEPHY_REF clocks
Device tree contains assigned-clock-rates property for these,
but default value will work just fine

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2023-03-19 14:12:00 +08:00
..
clk_pll.c clk: rockchip: pll: Add pll_rk3588 type for rk3588 2023-02-28 18:07:27 +08:00
clk_px30.c rockchip: clk: add watchdog clock to px30_clk_enable 2023-01-16 18:01:10 +08:00
clk_rk322x.c dm: Use access methods for dev/uclass private data 2021-01-05 12:24:40 -07:00
clk_rk3036.c dm: Use access methods for dev/uclass private data 2021-01-05 12:24:40 -07:00
clk_rk3066.c rockchip: rk3066: add clock driver for rk3066 soc 2022-04-18 11:25:13 +08:00
clk_rk3128.c rockchip: rk3128-cru: sync the clock dt-binding header from Linux 2022-12-19 10:56:12 +08:00
clk_rk3188.c treewide: Try to avoid the preprocessor with OF_REAL 2021-09-25 09:46:15 -06:00
clk_rk3288.c treewide: Try to avoid the preprocessor with OF_REAL 2021-09-25 09:46:15 -06:00
clk_rk3308.c treewide: Simply conditions with the new OF_REAL 2021-09-25 09:46:15 -06:00
clk_rk3328.c dm: Use access methods for dev/uclass private data 2021-01-05 12:24:40 -07:00
clk_rk3368.c treewide: Try to avoid the preprocessor with OF_REAL 2021-09-25 09:46:15 -06:00
clk_rk3399.c arm: rockchip: rk3399: Program PLL clock for DDR at 50 MHz in documented range 2022-10-19 19:30:48 +08:00
clk_rk3568.c clk: rockchip: rk3568: add stubs for CLK_PCIEPHY_REF clocks 2023-03-19 14:12:00 +08:00
clk_rk3588.c clk: rockchip: rk3588: Fix clk_aux16m in clock driver 2023-03-19 13:17:28 +08:00
clk_rv1108.c common: Drop asm/global_data.h from common header 2021-02-02 15:33:42 -05:00
clk_rv1126.c clk: rockchip: Add rv1126 clk support 2023-01-16 18:01:11 +08:00
Makefile clk: rockchip: Add rk3588 clk support 2023-02-28 18:07:27 +08:00