Pali Rohár 3bedbcc3aa arm: mvebu: a38x: serdes: Don't overwrite read-only SAR PCIe registers ... Device/Port Type bits of PCIe Root Port PCI Express Capabilities Register are read-only SAR registers and are initialized according to current mode configured by PCIe controller. Changing PCIe controller mode (from Root Complex mode to Endpoint mode or the other way) is possible via PCI Express Control Register (offset 0x41A00), bit 1 (ConfRoot Complex). This has to be done in PCIe controller driver (in our case pci_mvebu.c). Note that default mode is Root Complex. Maximum Link Speed bits of PCIe Root Port Link Capabilities Register are platform specific and overwriting them does not make sense. They are set by PCIe controller according to current SerDes configuration. For A38x it is 5.0 GT/s if SerDes supports appropriate speed. Maximum Link Width bits of PCIe Root Port Link Capabilities Register are read-only SAR registers, but unfortunately if this is not set correctly here, then access PCI config space of the endpoint card behind this Root Port does not work. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>		2021-10-08 08:33:52 +02:00
..
a38x	arm: mvebu: a38x: serdes: Don't overwrite read-only SAR PCIe registers	2021-10-08 08:33:52 +02:00
axp	common: Drop linux/delay.h from common header	2020-05-18 21:19:23 -04:00