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https://github.com/AsahiLinux/u-boot
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d8fa0a7668
Currently Makefile produces final mpc85xx image when SPL is not used in custom file u-boot-with-dtb.bin. It is quite confusing name as build process produce also intermediate file standard file u-boot-dtb.bin (which is just intermediate and not bootable). Other platforms use u-boot.bin (UBOOT_BIN) as standard name for final bootable raw image. So change Makefile rules and binman to produce final bootable file for mpc85xx also into file u-boot.bin. There is just need for mpc85xx to not define default rule for u-boot.bin then instruct binman (via DTS file) to store final image into u-boot.bin (instead of u-boot-with-dtb.bin) and finally rename target u-boot-with-dtb.bin to u-boot.bin. With this change are also removed custom Makefile hacks for mpc85xx that it produced non-standard output file. And also updated documentation. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Marek Behún <kabel@kernel.org>
64 lines
2.4 KiB
Text
64 lines
2.4 KiB
Text
Overview
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--------
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P1_P2_RDB_PC represents a set of boards including
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P1020MSBG-PC
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P1020RDB-PC
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P1020RDB-PD
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P1021RDB-PC
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P1024RDB
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P2020RDB-PC
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They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC
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has 64-bit DDR. All others have 32-bit DDR.
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Key features on these boards include:
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* DDR3
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* NOR flash
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* NAND flash (on RDB's only)
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* SPI flash (on RDB's only)
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* SDHC/MMC card slot
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* VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB)
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* PCIE slot and mini-PCIE slots
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As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM
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is used to store SPD data. In case of absent or corrupted SPD, falling back
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to timing data embedded in the source code will be used. Raw timing data is
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extracted from DDR chip datasheet. Different speeds of DDR are supported with
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this approach. ODT option is forced to fit this set of boards, again because
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they don't have regular DIMMs.
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CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification
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for writing timing.
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VSC firmware Address is defined by default in config file for eTSEC1.
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SD width is based off DIP switch. DIP switch is detected on the
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board by reading i2c bus and setting the appropriate mux values.
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Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have
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pins multiplexing. QE function needs to be disabled to access Nor Flash and
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CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
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in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
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enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below
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'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
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'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.
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Device tree support and how to enable it for different configs
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--------------------------------------------------------------
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Device tree support is available for p1020rdb and p2020rdb for below mentioned boot,
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1. NOR Boot
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2. NAND Boot
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3. SD Boot
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4. SPIFLASH Boot
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To enable device tree support for other boot, below configs need to be
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enabled in relative defconfig file,
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1. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required)
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2. CONFIG_OF_CONTROL
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3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
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CONFIG_RESET_VECTOR_ADDRESS - 0xffc
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If device tree support is enabled in defconfig,
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1. use 'u-boot.bin' for NOR boot.
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2. use 'u-boot-with-spl.bin' for other boot.
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