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f6457ce578
DRAM chip varies, and one code cannot satisfy all DRAMs. Add options to select a timing set. Currently only DDR3-1333 (the original set) is added into it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
238 lines
7.5 KiB
C
238 lines
7.5 KiB
C
/*
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* sun8i H3 platform dram controller register and constant defines
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*
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* (C) Copyright 2007-2015 Allwinner Technology Co.
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* Jerry Wang <wangflord@allwinnertech.com>
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* (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
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* (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
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* (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_DRAM_SUN8I_H3_H
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#define _SUNXI_DRAM_SUN8I_H3_H
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struct sunxi_mctl_com_reg {
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u32 cr; /* 0x00 control register */
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u32 cr_r1; /* 0x04 rank 1 control register (R40 only) */
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u8 res0[0x4]; /* 0x08 */
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u32 tmr; /* 0x0c (unused on H3) */
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u32 mcr[16][2]; /* 0x10 */
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u32 bwcr; /* 0x90 bandwidth control register */
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u32 maer; /* 0x94 master enable register */
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u32 mapr; /* 0x98 master priority register */
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u32 mcgcr; /* 0x9c */
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u32 cpu_bwcr; /* 0xa0 */
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u32 gpu_bwcr; /* 0xa4 */
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u32 ve_bwcr; /* 0xa8 */
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u32 disp_bwcr; /* 0xac */
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u32 other_bwcr; /* 0xb0 */
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u32 total_bwcr; /* 0xb4 */
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u8 res1[0x8]; /* 0xb8 */
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u32 swonr; /* 0xc0 */
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u32 swoffr; /* 0xc4 */
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u8 res2[0x8]; /* 0xc8 */
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u32 cccr; /* 0xd0 */
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u8 res3[0x54]; /* 0xd4 */
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u32 mdfs_bwlr[3]; /* 0x128 (unused on H3) */
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u8 res4[0x6cc]; /* 0x134 */
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u32 protect; /* 0x800 */
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};
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#define MCTL_CR_BL8 (0x4 << 20)
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#define MCTL_CR_1T (0x1 << 19)
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#define MCTL_CR_2T (0x0 << 19)
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#define MCTL_CR_LPDDR3 (0x7 << 16)
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#define MCTL_CR_LPDDR2 (0x6 << 16)
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#define MCTL_CR_DDR3 (0x3 << 16)
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#define MCTL_CR_DDR2 (0x2 << 16)
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#define MCTL_CR_SEQUENTIAL (0x1 << 15)
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#define MCTL_CR_INTERLEAVED (0x0 << 15)
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#define MCTL_CR_FULL_WIDTH (0x1 << 12)
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#define MCTL_CR_HALF_WIDTH (0x0 << 12)
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#define MCTL_CR_BUS_FULL_WIDTH(x) ((x) << 12)
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#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8)
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#define MCTL_CR_ROW_BITS(x) (((x) - 1) << 4)
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#define MCTL_CR_EIGHT_BANKS (0x1 << 2)
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#define MCTL_CR_FOUR_BANKS (0x0 << 2)
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#define MCTL_CR_DUAL_RANK (0x1 << 0)
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#define MCTL_CR_SINGLE_RANK (0x0 << 0)
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/*
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* CR_R1 is a register found in the R40's DRAM controller. It sets various
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* parameters for rank 1. Bits [11:0] have the same meaning as the bits in
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* MCTL_CR, but they apply to rank 1 only. This implies we can have
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* different chips for rank 1 than rank 0.
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*
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* As address line A15 and CS1 chip select for rank 1 are muxed on the same
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* pin, if single rank is used, A15 must be muxed in.
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*/
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#define MCTL_CR_R1_MUX_A15 (0x1 << 21)
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#define PROTECT_MAGIC (0x94be6fa3)
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struct sunxi_mctl_ctl_reg {
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u32 pir; /* 0x00 PHY initialization register */
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u32 pwrctl; /* 0x04 */
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u32 mrctrl; /* 0x08 */
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u32 clken; /* 0x0c */
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u32 pgsr[2]; /* 0x10 PHY general status registers */
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u32 statr; /* 0x18 */
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u8 res1[0x10]; /* 0x1c */
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u32 lp3mr11; /* 0x2c */
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u32 mr[4]; /* 0x30 mode registers */
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u32 pllgcr; /* 0x40 */
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u32 ptr[5]; /* 0x44 PHY timing registers */
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u32 dramtmg[9]; /* 0x58 DRAM timing registers */
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u32 odtcfg; /* 0x7c */
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u32 pitmg[2]; /* 0x80 PHY interface timing registers */
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u8 res2[0x4]; /* 0x88 */
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u32 rfshctl0; /* 0x8c */
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u32 rfshtmg; /* 0x90 refresh timing */
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u32 rfshctl1; /* 0x94 */
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u32 pwrtmg; /* 0x98 */
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u8 res3[0x1c]; /* 0x9c */
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u32 vtfcr; /* 0xb8 (unused on H3) */
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u32 dqsgmr; /* 0xbc */
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u32 dtcr; /* 0xc0 */
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u32 dtar[4]; /* 0xc4 */
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u32 dtdr[2]; /* 0xd4 */
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u32 dtmr[2]; /* 0xdc */
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u32 dtbmr; /* 0xe4 */
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u32 catr[2]; /* 0xe8 */
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u32 dtedr[2]; /* 0xf0 */
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u8 res4[0x8]; /* 0xf8 */
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u32 pgcr[4]; /* 0x100 PHY general configuration registers */
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u32 iovcr[2]; /* 0x110 */
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u32 dqsdr; /* 0x118 */
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u32 dxccr; /* 0x11c */
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u32 odtmap; /* 0x120 */
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u32 zqctl[2]; /* 0x124 */
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u8 res6[0x14]; /* 0x12c */
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u32 zqcr; /* 0x140 ZQ control register */
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u32 zqsr; /* 0x144 ZQ status register */
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u32 zqdr[3]; /* 0x148 ZQ data registers */
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u8 res7[0x6c]; /* 0x154 */
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u32 sched; /* 0x1c0 */
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u32 perfhpr[2]; /* 0x1c4 */
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u32 perflpr[2]; /* 0x1cc */
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u32 perfwr[2]; /* 0x1d4 */
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u8 res8[0x24]; /* 0x1dc */
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u32 acmdlr; /* 0x200 AC master delay line register */
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u32 aclcdlr; /* 0x204 AC local calibrated delay line register */
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u32 aciocr; /* 0x208 AC I/O configuration register */
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u8 res9[0x4]; /* 0x20c */
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u32 acbdlr[31]; /* 0x210 AC bit delay line registers */
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u8 res10[0x74]; /* 0x28c */
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struct { /* 0x300 DATX8 modules*/
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u32 mdlr; /* 0x00 master delay line register */
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u32 lcdlr[3]; /* 0x04 local calibrated delay line registers */
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u32 bdlr[11]; /* 0x10 bit delay line registers */
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u32 sdlr; /* 0x3c output enable bit delay registers */
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u32 gtr; /* 0x40 general timing register */
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u32 gcr; /* 0x44 general configuration register */
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u32 gsr[3]; /* 0x48 general status registers */
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u8 res0[0x2c]; /* 0x54 */
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} dx[4];
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u8 res11[0x388]; /* 0x500 */
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u32 upd2; /* 0x888 */
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};
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#define PTR3_TDINIT1(x) ((x) << 20)
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#define PTR3_TDINIT0(x) ((x) << 0)
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#define PTR4_TDINIT3(x) ((x) << 20)
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#define PTR4_TDINIT2(x) ((x) << 0)
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#define DRAMTMG0_TWTP(x) ((x) << 24)
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#define DRAMTMG0_TFAW(x) ((x) << 16)
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#define DRAMTMG0_TRAS_MAX(x) ((x) << 8)
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#define DRAMTMG0_TRAS(x) ((x) << 0)
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#define DRAMTMG1_TXP(x) ((x) << 16)
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#define DRAMTMG1_TRTP(x) ((x) << 8)
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#define DRAMTMG1_TRC(x) ((x) << 0)
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#define DRAMTMG2_TCWL(x) ((x) << 24)
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#define DRAMTMG2_TCL(x) ((x) << 16)
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#define DRAMTMG2_TRD2WR(x) ((x) << 8)
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#define DRAMTMG2_TWR2RD(x) ((x) << 0)
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#define DRAMTMG3_TMRW(x) ((x) << 16)
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#define DRAMTMG3_TMRD(x) ((x) << 12)
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#define DRAMTMG3_TMOD(x) ((x) << 0)
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#define DRAMTMG4_TRCD(x) ((x) << 24)
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#define DRAMTMG4_TCCD(x) ((x) << 16)
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#define DRAMTMG4_TRRD(x) ((x) << 8)
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#define DRAMTMG4_TRP(x) ((x) << 0)
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#define DRAMTMG5_TCKSRX(x) ((x) << 24)
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#define DRAMTMG5_TCKSRE(x) ((x) << 16)
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#define DRAMTMG5_TCKESR(x) ((x) << 8)
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#define DRAMTMG5_TCKE(x) ((x) << 0)
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#define RFSHTMG_TREFI(x) ((x) << 16)
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#define RFSHTMG_TRFC(x) ((x) << 0)
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#define PIR_CLRSR (0x1 << 27) /* clear status registers */
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#define PIR_QSGATE (0x1 << 10) /* Read DQS gate training */
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#define PIR_DRAMINIT (0x1 << 8) /* DRAM initialization */
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#define PIR_DRAMRST (0x1 << 7) /* DRAM reset */
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#define PIR_PHYRST (0x1 << 6) /* PHY reset */
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#define PIR_DCAL (0x1 << 5) /* DDL calibration */
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#define PIR_PLLINIT (0x1 << 4) /* PLL initialization */
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#define PIR_ZCAL (0x1 << 1) /* ZQ calibration */
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#define PIR_INIT (0x1 << 0) /* PHY initialization trigger */
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#define PGSR_INIT_DONE (0x1 << 0) /* PHY init done */
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#define ZQCR_PWRDOWN (1U << 31) /* ZQ power down */
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#define ACBDLR_WRITE_DELAY(x) ((x) << 8)
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#define DXBDLR_DQ(x) (x) /* DQ0-7 BDLR index */
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#define DXBDLR_DM 8 /* DM BDLR index */
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#define DXBDLR_DQS 9 /* DQS BDLR index */
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#define DXBDLR_DQSN 10 /* DQSN BDLR index */
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#define DXBDLR_WRITE_DELAY(x) ((x) << 8)
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#define DXBDLR_READ_DELAY(x) ((x) << 0)
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/*
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* The delay parameters below allow to allegedly specify delay times of some
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* unknown unit for each individual bit trace in each of the four data bytes
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* the 32-bit wide access consists of. Also three control signals can be
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* adjusted individually.
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*/
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#define BITS_PER_BYTE 8
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#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
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/* The eight data lines (DQn) plus DM, DQS and DQSN */
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#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3)
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struct dram_para {
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u16 page_size;
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u8 bus_full_width;
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u8 dual_rank;
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u8 row_bits;
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u8 bank_bits;
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const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
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const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
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const u8 ac_delays[31];
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};
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static inline int ns_to_t(int nanoseconds)
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{
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const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
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return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
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}
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void mctl_set_timing_params(uint16_t socid, struct dram_para *para);
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#endif /* _SUNXI_DRAM_SUN8I_H3_H */
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