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14e4b14979
Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
138 lines
3.8 KiB
C
138 lines
3.8 KiB
C
/*
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* Copyright (c) 2016 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_SDRAM_AST2500_H
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#define _ASM_ARCH_SDRAM_AST2500_H
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#define SDRAM_UNLOCK_KEY 0xfc600309
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#define SDRAM_VIDEO_UNLOCK_KEY 0x2003000f
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#define SDRAM_PCR_CKE_EN (1 << 0)
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#define SDRAM_PCR_AUTOPWRDN_EN (1 << 1)
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#define SDRAM_PCR_CKE_DELAY_SHIFT 4
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#define SDRAM_PCR_CKE_DELAY_MASK 7
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#define SDRAM_PCR_RESETN_DIS (1 << 7)
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#define SDRAM_PCR_ODT_EN (1 << 8)
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#define SDRAM_PCR_ODT_AUTO_ON (1 << 10)
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#define SDRAM_PCR_ODT_EXT_EN (1 << 11)
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#define SDRAM_PCR_TCKE_PW_SHIFT 12
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#define SDRAM_PCR_TCKE_PW_MASK 7
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#define SDRAM_PCR_RGAP_CTRL_EN (1 << 15)
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#define SDRAM_PCR_MREQI_DIS (1 << 17)
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/* Fixed priority DRAM Requests mask */
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#define SDRAM_REQ_VGA_HW_CURSOR (1 << 0)
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#define SDRAM_REQ_VGA_TEXT_CG_FONT (1 << 1)
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#define SDRAM_REQ_VGA_TEXT_ASCII (1 << 2)
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#define SDRAM_REQ_VGA_CRT (1 << 3)
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#define SDRAM_REQ_SOC_DC_CURSOR (1 << 4)
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#define SDRAM_REQ_SOC_DC_OCD (1 << 5)
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#define SDRAM_REQ_SOC_DC_CRT (1 << 6)
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#define SDRAM_REQ_VIDEO_HIPRI_WRITE (1 << 7)
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#define SDRAM_REQ_USB20_EHCI1 (1 << 8)
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#define SDRAM_REQ_USB20_EHCI2 (1 << 9)
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#define SDRAM_REQ_CPU (1 << 10)
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#define SDRAM_REQ_AHB2 (1 << 11)
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#define SDRAM_REQ_AHB (1 << 12)
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#define SDRAM_REQ_MAC0 (1 << 13)
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#define SDRAM_REQ_MAC1 (1 << 14)
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#define SDRAM_REQ_PCIE (1 << 16)
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#define SDRAM_REQ_XDMA (1 << 17)
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#define SDRAM_REQ_ENCRYPTION (1 << 18)
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#define SDRAM_REQ_VIDEO_FLAG (1 << 21)
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#define SDRAM_REQ_VIDEO_LOW_PRI_WRITE (1 << 28)
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#define SDRAM_REQ_2D_RW (1 << 29)
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#define SDRAM_REQ_MEMCHECK (1 << 30)
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#define SDRAM_ICR_RESET_ALL (1 << 31)
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#define SDRAM_CONF_CAP_SHIFT 0
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#define SDRAM_CONF_CAP_MASK 3
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#define SDRAM_CONF_DDR4 (1 << 4)
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#define SDRAM_CONF_SCRAMBLE (1 << 8)
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#define SDRAM_CONF_SCRAMBLE_PAT2 (1 << 9)
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#define SDRAM_CONF_CACHE_EN (1 << 10)
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#define SDRAM_CONF_CACHE_INIT_EN (1 << 12)
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#define SDRAM_CONF_DUALX8 (1 << 13)
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#define SDRAM_CONF_CACHE_INIT_DONE (1 << 19)
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#define SDRAM_CONF_CAP_128M 0
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#define SDRAM_CONF_CAP_256M 1
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#define SDRAM_CONF_CAP_512M 2
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#define SDRAM_CONF_CAP_1024M 3
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#define SDRAM_MISC_DDR4_TREFRESH (1 << 3)
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#define SDRAM_PHYCTRL0_INIT (1 << 0)
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#define SDRAM_PHYCTRL0_AUTO_UPDATE (1 << 1)
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#define SDRAM_PHYCTRL0_NRST (1 << 2)
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#define SDRAM_REFRESH_CYCLES_SHIFT 0
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#define SDRAM_REFRESH_CYCLES_MASK 0xf
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#define SDRAM_REFRESH_ZQCS_EN (1 << 7)
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#define SDRAM_REFRESH_PERIOD_SHIFT 8
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#define SDRAM_REFRESH_PERIOD_MASK 0xf
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#define SDRAM_TEST_LEN_SHIFT 4
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#define SDRAM_TEST_LEN_MASK 0xfffff
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#define SDRAM_TEST_START_ADDR_SHIFT 24
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#define SDRAM_TEST_START_ADDR_MASK 0x3f
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#define SDRAM_TEST_EN (1 << 0)
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#define SDRAM_TEST_MODE_SHIFT 1
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#define SDRAM_TEST_MODE_MASK 3
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#define SDRAM_TEST_MODE_WO 0
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#define SDRAM_TEST_MODE_RB 1
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#define SDRAM_TEST_MODE_RW 2
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#define SDRAM_TEST_GEN_MODE_SHIFT 3
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#define SDRAM_TEST_GEN_MODE_MASK 7
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#define SDRAM_TEST_TWO_MODES (1 << 6)
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#define SDRAM_TEST_ERRSTOP (1 << 7)
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#define SDRAM_TEST_DONE (1 << 12)
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#define SDRAM_TEST_FAIL (1 << 13)
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#define SDRAM_AC_TRFC_SHIFT 0
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#define SDRAM_AC_TRFC_MASK 0xff
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#ifndef __ASSEMBLY__
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struct ast2500_sdrammc_regs {
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u32 protection_key;
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u32 config;
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u32 gm_protection_key;
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u32 refresh_timing;
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u32 ac_timing[3];
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u32 misc_control;
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u32 mr46_mode_setting;
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u32 mr5_mode_setting;
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u32 mode_setting_control;
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u32 mr02_mode_setting;
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u32 mr13_mode_setting;
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u32 power_control;
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u32 req_limit_mask;
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u32 pri_group_setting;
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u32 max_grant_len[4];
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u32 intr_ctrl;
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u32 ecc_range_ctrl;
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u32 first_ecc_err_addr;
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u32 last_ecc_err_addr;
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u32 phy_ctrl[4];
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u32 ecc_test_ctrl;
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u32 test_addr;
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u32 test_fail_dq_bit;
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u32 test_init_val;
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u32 phy_debug_ctrl;
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u32 phy_debug_data;
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u32 reserved1[30];
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u32 scu_passwd;
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u32 reserved2[7];
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u32 scu_mpll;
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u32 reserved3[19];
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u32 scu_hwstrap;
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};
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_ARCH_SDRAM_AST2500_H */
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