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The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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| .. | ||
| fsl-layerscape | ||
| hisilicon | ||
| zynqmp | ||
| cache.S | ||
| cache_v8.c | ||
| config.mk | ||
| cpu.c | ||
| exceptions.S | ||
| fwcall.c | ||
| generic_timer.c | ||
| Kconfig | ||
| Makefile | ||
| start.S | ||
| tlb.S | ||
| transition.S | ||
| u-boot-spl.lds | ||
| u-boot.lds | ||